United Microelectronics Corp.

Other

Infineon Technologies Ag

Gwo-Shii Yang

Tri-Rung Yew

Water Lur

Hsueh-Chung Chen

Chih-Chien Liu

Chiung-Sheng Hsiung

Kuo-Tai Huang

Tong-Yu Chen

Coming Chen

Hsueh-Hao Shih

Wen-Yi Hsieh

Kun-Chi Lin

Sung-Hsiung Wang

Michael W C Huang

Wayne Tan

Chih-Chao Yang

Hans-Joachim Barth

Erdem Kaltalioglu

Juan-Yuan Wu

Shahab Siddiqui

Darryl D Restaino

Cheng-Yuan Tsai

Jen Hui Chen

Hsien-Ta Chung

Hsiao-Ling Lu

Delores A Bennett

Chien Chao Huang

Yi-Min Huang

Michael Wc Huang

Chih-Chih Liu

Yi-hsiung Lin

James Cc Huang

Application of an adhesion promoter to a cap layer and oxidation of the adhesion promoter prior to deposition of an organic interlevel dielectric thereon reduces via resistance problems during thermal cycles of semiconductor wafers embodying multiple levels of metal and organic interlevel dielectrics.

Method for eliminating via resistance shift in organic ILD

A process for forming fusible links in an integrated circuit in which the fusible links are formed in the final metallization layer simultaneously with bonding pads. The process can be applied in the fabrication of integrated circuits that employ copper metallization and low k dielectric materials. After patterning the final metal (aluminum) layer to form the fusible links and the bonding pads, a dielectric etch stop layer is formed over the final metal layer before a passivation layer is deposited. The passivation layer is removed in areas over the fusible links and the bonding pads. The dielectric etch stop layer is removed either from above the bonding pads only, or from above both the bonding pads and the fusible links.

Process for forming fusible links

The present invention provides a method for forming low dielectric constant inter-metal dielectric layer. The method comprises providing a semiconductor substrate and forming a first dielectric layer on the semiconductor substrate. Conductor structures are formed in the first dielectric layer. The partial first dielectric layer is removed by using the conductor structures as etch mask. A second dielectric layer is formed between the conductor structure, which has a dielectric constant smaller than the first dielectric layer. The semiconductor structure comprises a substrate, a first dielectric layer on the substrate, multitude of conductor structures in the first dielectric layer, and multitude of second dielectric structures in the first dielectric layer and between the conductor structures.

Method for forming interconnect structure with low dielectric constant

A method for forming a three dimensional semiconductor structure which has vertical capacitor(s) but not horizontal capacitor(s). The method essentially at least includes these steps of forming bottom plates within dielectric layers, forming another dielectric layer over bottom plates, removing all dielectric layers over bottom plates, forming optional liner(s) and capacitor dielectric layers on bottom plates, and forming top plates over capacitor dielectric layers. Note that shape of bottom plates is alike to the bottom connection and verticle fingers, also note that each gap within bottom plates is filled by both capacitor dielectric layer and top plate.

Method for forming three dimensional semiconductor structure and three dimensional capacitor

A method for fabricating a semiconductor device. A shallow trench isolation is formed by forming a well region, a gate oxide layer and a wiring layer prior to forming a trench in the substrate. The trench is then filled with silicon oxide layer doped with germanium, nitrogen, titanium or other refractory metal. In addition, a MOS device is also fabricated with a gate buried in the substrate with a shallow trench isolation filled with the doped silicon oxide layer formed therein.

Method of fabricating semiconductor device

Method of fabricating a shallow trench isolation semiconductor device

A method for fabricating, a shallow trench isolation structure. A pad oxide layer and a silicon nitride layer are formed in sequence on a substrate. A trench is formed in the substrate and a liner oxide layer is formed on a sidewall of the trench. A doped silicon dioxide layer is formed on the silicon nitride layer and fills the trench. An annealing process is performed to density the doped silicon dioxide layer. A portion of the doped silicon dioxide layer is removed to expose the silicon nitride layer by a planarization process.

Method for fabricating shallow trench isolation structure

A method for forming borderless contact is disclosed. The method includes providing a substrate with active areas and a trench isolation region in which the active areas are silcide. Then, the substrate is nitridized such that a titanium nitride layer is formed on the active areas and a silicon oxynitride is formed on the trench isolation region. A dielectric layer is deposited on the substrate and an opening is etched in the dielectric layer in which the opening overlies both a portion of the trench isolation region and a portion of the active area.

Method of forming borderless contact

A method for manufacturing a metal oxide semiconductor transistor having a raised source/drain is described. A first spacer is formed on a sidewall of a gate electrode. An epitaxial layer is then formed on the exposed surface of the substrate and a top surface of the gate electrode. A light implantation step is then performed on the substrate while using the gate electrode and the first spacer as a first mask. Thereafter, a second spacer is formed on the sidewall of the gate electrode. A heavy implantation step is then performed on the substrate while using the gate electrode, the first spacer and the second spacer as a second mask. The epitaxial layer is then formed before the forming of the extension structure of the source/drain. Therefore, dopants in a source/drain extension structure avoid suffering the high temperature needed to form the epitaxial layer so that the redistribution of the dopants is prevented.

Method for manufacturing metal oxide semiconductor transistor having raised source/drain

A method of manufacturing shallow trench isolation structures. The method includes the steps of depositing insulating material into the trench of a substrate to form an insulation layer. The substrate has a plurality of active regions, each occupying a different area and having different sizes. In addition, there is a silicon nitride layer on top of each active region. Thereafter, a photoresist layer is then deposited over the insulation layer. Next, a portion of the photoresist layer is etched back to expose a portion of the oxide layer so that the remaining photoresist material forms a cap layer over the recessed area of the insulation layer. Subsequently, using the photoresist cap layer as a mask, the insulation layer is etched to remove a portion of the exposed oxide layer, thereby forming trenches within the oxide layer. After that, the photoresist cap layer is removed. Finally, a chemical-mechanical polishing operation is carried out to polish the insulation layer until the silicon nitride layer is exposed.

Method of manufacturing shallow trench isolation

A method of testing a leakage current caused by a self-aligned silicide process is described. The invention uses different test structure to monitor degree of and reason for a leakage current caused by a self-aligned silicide process. While monitoring a self-aligned silicide process performed on a metal-oxide semiconductor transistor without a LDD region, in addition to considering a leakage current occurring from the metal silicide layer to the junction and occurring at edge of the metal silicide layer, the invention further considers a leakage current at comer of the metal silicide layer. For a metal-oxide semiconductor transistor having a LDD region, the invention further considers a leakage current from the metal silicide layer to the LDD region. The invention monitors a leakage current at comer of the metal silicide layer.

Method for testing leakage current caused self-aligned silicide

A method of fabricating a shallow trench isolation structure is described. A preserve layer is formed on a substrate. A trench is formed in the substrate and the preserve layer. An oxide layer is formed over the substrate to fill the trench. A wet densification step is performed in a moist environment. A planarization step is performed until the preserve layer is exposed. A shallow trench isolation structure is formed.

Method of fabricating shallow trench isolation structure

A process of forming a silicide on a source/drain region of a MOS device is described, wherein the MOS device has a gate spacer partially covering the source/drain region. A silicon film is formed on the source/drain region, wherein the silicon film has a portion near the gate spacer substantially thinner than the other portion of the silicon film. The silicon film is reacted with a metal film to wholly consume the portion of the silicon film near the gate spacer and to partially consume the other portion of the silicon film.

Process of forming self-aligned silicide on source/drain region

A method of fabricating a shallow trench isolation structure is described. A mask layer is formed on the substrate. The mask layer and the substrate are patterned to form trenches in the substrate. The trenches comprise a smallest trench. A first isolation layer is formed on the mask layer to fill partially the trenches. A densification step is performed. A second isolation layer is formed on the first isolation layer to fill completely the trench. The first isolation layer and the second isolation layer are removed until the mask layer is exposed. The mask layer is removed.

A method of fabricating a DRAM capacitor includes the step of forming an insulated layer and an etching stop layer successively on a substrate having a device structure. A contact window is formed within the etching stop layer and the insulated layer. A conductive layer is formed on the etching layer to fill in the contact window and patterned to serve as a lower electrode of the capacitor. A highly doped dielectric layer is then formed on the lower electrode and a thermal process is performed to diffuse the dopants inside the highly doped dielectric layer into the surface of the lower electrode. The dielectric layer is removed. A capacitor dielectric layer and an upper electrode are successively formed on the lower electrode to complete the fabrication of the capacitor.

Growing community of inventors

Hsin-Chu, Taiwan

Gwo-Shii Yang