International Business Machines Corporation

Globalfoundries Inc.

Gustavo Enrique Tellez

Gi-Joon Nam

Diwesh Pandey

Lakshmi Narasimha Reddy

Jason D Hibbeler

John Maxwell Cohn

Hua Xiang

Robert J Allen

Stephen Thomas Quay

Ying Zhou

Jiang Hu

Paul Gerard Villarrubia

Shyam Ramji

Alexey Y Lvov

Peter Anton Habitz

Paul Steven Zuchowski

Michael S Gray

Kevin W McCullen

Andrew D Huber

Christian Schulte

Paul H Bergeron

Lars W Liebmann

Zhuo Li

Mark Alan Lavin

Scott Whitney Gould

Fook-Luen Heng

Juergen Koehl

Daniel Nelson Maynard

Sven Peyer

Ivan L Wemple

Robert F Walker

Benjamin Neil Trombley

Jinwook Jung

Archibald John Allen

Michael Richard Ouellette

Charles Jay Alpert

Eric A Foreman

Dennis Merton Newns

Shuo Zhang

Yaoguang Wei

Christopher J Berry

Michael H Wood

Natarajan Viswanathan

Adam P Matheny

Gary S Ditlow

Robert Alan Philhower

Douglas Wayne Kemerer

Alexander Ivrii

Zhichao Li

Tina Jane Wagner

Evanthia Papadopoulou

Jeanne P S Bickford

Leah M Pastel

Vassilios Constantinos Gerousis

Jarrod Alexander Roy

Matthew Thomas Guzowski

Daria Rose Dooling

Ralph James Williams

Rani Narayan

Michael Alexander Bowen

David Erin Moran

Wilm Ernst Donath

Michael Kazda

Philip S Honsinger

Stefanus Mantik

Frank Musante

Cindy ShuiKing Washburn

Taraneh Taghavi

Lijiang L Wang

Thomas Wood Wilkins

Reginald B Wilcox, Jr

Karsten Muuss

Charles L Meiley

Steven G Lovejoy

Gary R Doyle

Richard L Moore

Zhan Chen

Gorden S Starkey

Rongjian Liang

Alan Dziedzic

Joseph Koone

Michael Gester

Andre Hogan

Robert R Arelt

Smitha Reddy

Karl W Vinson

James Leland

Shaodi Gao

Jennifer Kazda

Peter S Wissell

Sriram Peri

Design rule violations ('DRVs') may be predicted using a design rule check (“DRC”) density map during a physical synthesis operation prior to executing a routing operation.

Rule check heatmap prediction

Embodiments are provided for providing enhanced routing in a computing system by a processor. One or more of a plurality of short nets in a cell of an integrated circuit may be aligned for executing a routing operation, wherein a short net is a two-pin net having two gates on adjacent rows having a horizontal distance less than a selected threshold.

Short net pin alignment for routing

Embodiments are provided for providing power staple avoidance during routing in a computing system by a processor. One or more transistor gates may be shifted in each row of an integrated circuit to avoid alignment of cell pins and power staples for executing a routing operation, where the circuit row is partitioned into segments based on one or more fixed objects.

Power staple avoidance for routing via reduction

One or more line ends of a putative integrated circuit design are modelled using a constraint graph. A longest path algorithm is applied on subgraphs of the constraint graph. An extent minimization algorithm is carried out on the subgraphs of the constraint graph and routing on the putative integrated circuit design is carried out based on results of the longest path algorithm and the extent minimization algorithm.

Technology-independent line end routing

A constraint graph for a candidate routing solution is created; each node in the graph represents a position of an end of a metal shape and each arc in the graph represents a design rule constraint between two of the nodes. A solution graph is computed, for at least a portion of the constraint graph, using a shape processing algorithm. The solution graph is checked for design rule violations to generate one or more violation graphs. A constraint window and a selection of one or more arcs for at least one of the violation graphs are generated. The candidate routing solution is revised, based on one or more violated design rules corresponding to at least one of the selected arcs within the constraint window. Optionally, an integrated circuit is fabricated in accordance with the revised solution.

Fast independent checker for extreme ultraviolet (EUV) routing

Methods and systems of routing a design layout include setting an inner region and an outer region for modification of structures in an original design layout, in accordance with a minimum spacing that is based on a fabrication process. Routing of trim positions and conductive wire extents is performed within the inner region, based on positions of shapes within the outer region, including node folding of a new constraint graph to minimize perturbations from a previous constraint graph, to generate an updated design layout that can be manufactured using the fabrication process.

Region-based layout routing

Aspects of the invention include systems and methods for implementing a sweepline triangulation technique to optimize spanning graphs for circuit routing. A non-limiting example computer-implemented method includes receiving an unrouted net having a plurality of elements. The elements can include pins, vias, and wires. A sweepline is passed across the unrouted net until the sweepline intersects an element of the plurality of elements. In response to the sweepline intersecting the element, the sweepline is stopped and one or more nodes on the sweepline and one or more previous nodes are identified. A connectivity graph is built from the one or more nodes and the one or more previous nodes. The connectivity graph includes one or more arcs and one or more guides. A minimum spanning tree is built by removing one or more guides from the connectivity graph and the unrouted net is routed based on the minimum spanning tree.

Sweepline triangulation for spanning graphs

Aspects of the invention include generating a set of via mesh specifications for a cell within an integrated circuit. Each via mesh specification defines one or more straps on each layer above a first layer, which includes one or more pins that form a pin terminal, to a top layer that connects the cell to a net for interconnection of the cell with one or more other cells, and also one or more vias that interconnect adjacent ones of the layers. Aspects also include verifying whether each via mesh specification is a universally routable via mesh specification guaranteeing that the cell interconnects with other cells through the net while meeting all design rules, and including only the via mesh specifications of the set of via mesh specifications that are universally routable in a library of via mesh specifications. The library is used to finalize and fabricate the integrated circuit.

Generation and selection of universally routable via mesh specifications in an integrated circuit

A method for enhancing routability in a cell-based design includes: obtaining a layout corresponding to a placement of cells in the cell-based design; identifying one or more areas of the layout where routability is predicted to be constrained; selectively adding white spaces to the identified one or more areas of the layout where routability is predicted to be constrained to thereby generate a modified layout; legalizing placement of the modified layout; and running a detailed routing on the modified layout.

White space insertion for enhanced routability

Techniques for dynamically generating self-aligned double patterning (SADP) gate regions based on gate distribution and the relocation of the gates to their matched region are provided. In one aspect, a method for generating SADP gate regions in a circuit design includes: obtaining a circuit design having SADP gates, and a placement solution for the SADP gates that, while non-overlapping, violates SADP track routing matching requirements; determining approximate locations of SADP regions in the circuit design; assigning the SADP gates to the SADP regions using a minimum-cost maximum-flow (min-cost max-flow) process; and identifying, once all of the SADP gates have been assigned to the SADP regions, non-overlapping locations for the SADP gates in the SADP regions.

Dynamic SADP region generation

For each of a plurality of source-sink pairs, a corresponding interconnect layer is selected having a reach length which permits propagation of a required signal within a required sink cycle delay. For a first clock cycle, a movable region for a first latch is located as a first plurality of overlapped regions one reach length from a source and the required sink cycle delay number of reach lengths from each one of the sinks; and the first plurality of overlapped regions is represented as nodes on a first cycle level of a topology search graph. Analogous actions are carried out for a second clock cycle of the required sink cycle delay. A latch tree is created based on the topology search graph, wherein a required number of latches is minimized, and at each of the cycle levels, all sinks of source nodes selected at a previous level are covered.

Multi-cycle latch tree synthesis

A global router determines edge capacity of global tiles for a first integrated circuit in a global routing operation. The global router determines a respective edge capacity of first width wire tracks for each of a plurality of global tiles in a first metal layer in the first integrated circuit in a first global routing operation. The global router determines a respective edge capacity of second width wire tracks for each of the plurality of global tiles in the first metal layer in the first integrated circuit in a second global routing operation. The edge capacities for first width and second width wire tracks are determined in separate operations by the global router as part of the operations performed for fabrication of the first integrated circuit.

Capacity model for global routing

Techniques regarding functional placement of one or more logic gates in a periodic circuit row configuration are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an optimization component, operatively coupled to the processor, that can determine functional placement of a logic gate in a self-aligned double patterning process that can form a periodic circuit row configuration.

Autonomous placement to satisfy self-aligned double patterning constraints

A method of performing physical design of an integrated circuit includes subdividing each metal layer of a plurality of metal layers of the integrated circuit into a plurality of g-cells. Each metal layer has either horizontal or vertical tracks, the g-cells of the metal layers with horizontal tracks have vertical edges between adjacent ones of the g-cells, and the g-cells of the metal layers with vertical tracks have horizontal edges between adjacent ones of the g-cells. The method includes determining congestion for each metal layer as congestion values associated with the horizontal edges or the vertical edges of the metal layer, identifying hotspots for each metal layer based on the congestion values of the metal layer, determining a penalty associated with the hotspots of each metal layer, determining a congestion metric for each metal layer based on the penalty, and performing routing of the wires based on the congestion metric.

Identification of hotspots in congestion analysis during physical design of integrated circuit

A method of generating a routing result to manufacture an integrated circuit using self-aligned double patterning includes generating an initial routing result that indicates a location and length of connections between components, and generating an initial constraint graph with trim shapes indicating gaps in the connections being represented as nodes and with arcs indicating relative position constraints between a pair of the nodes. The method also includes subdividing the initial constraint graph into two or more subgraphs, determining a final position of each of the nodes in the two or more subgraphs, and generating a routed design with the trim shapes having the final position of corresponding ones of the nodes relative to the connections and with extents filling in spaces between one or more of the trim shapes and associated connections. The routed design is provided for manufacture of the integrated circuit.

Self-aligned double patterning-aware routing in chip manufacturing

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Essex Junction, VT, United States of America

Gustavo Enrique Tellez