International Business Machines Corporation

Medical University of South Carolina

Georgia Tech Research Corporation

Ngimat Co.

Guoan Wang

Wayne Harvey Woods, Jr

Essam Mina

Hanyi Ding

Barbara S DeWitt

B M Farid Rahman

Jiansheng Xu

Sanjib Sur

Srihari Nelakuditi

Amit Bavisi

Bm Farid Rahman

Jinqun Ge

Timothy Harrison Daubenspeck

Wolfgang Sauter

Andrew Tye Hunt

Emmanouil Tentzeris

Pinping Sun

Todd A Polley

Kwan Him Lam

Ioannis Papapolymerou

RongLin Li

Dane R Thompson

Nickolas D Kingsley

Ramanan Bairavasubramanian

Gerald DeJean

Ioannis (John) Papapolymerou

Tengxing Wang

Michael P Keene

Described herein are systems and methods for a design method and new interconnect structures with incorporated interdigital trapezoidal tabs structures enabled with materials with either larger permittivity or permeability for improved signal integrity.

Method and design of high-performance interconnects with improved signal integrity

An antenna assembly includes an antenna and a heatsink. The antenna may be configured to support radio communications and generate heat, and may include a forward antenna surface configured to transmit or receive communications signals and a rear antenna surface that is affixed to a substrate. The heatsink structure may be positioned to be within a forward electromagnetic field that is emitted from the forward antenna surface and away from the rear antenna surface. The heatsink structure may be configured to perform a convection operation between the antenna and a fluid to perform thermal dissipation of the heat from the antenna.

Heat dissipating antenna structures

An electrically tunable radio frequency phase shifter with compact 3-D structure that integrates both ferromagnetic and ferroelectric materials, and utilizes 3-D structure to increase the tuning efficiency and achieve miniaturization.

Dually electrically tunable 3-D compact RF phase shifter

A reconfigurable antenna apparatus may include an antenna assembly and control circuitry. The antenna assembly may include an antenna patch array having a plurality of antenna patches and a switch array having plurality of switches. Each switch of the plurality switches may be electronically controllable to transition between states including a conducting state and a non-conducting state. Each switch may be electrically connected between two of the antenna patches of the antenna array. The control circuitry may be configured to control the states of the switches of the switch array to operate the antenna patch array in a first communications mode at a first wavelength, and control the states of the switches of the switch array to operate the antenna patch array in a second communications mode at a second wavelength.

Reconfigurable antenna design for centimeter-wave and millimeter-wave

The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture. The structure includes a plurality of through silicon vias and conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias. A first through silicon via of the plurality of through silicon vias forms a first port of a three dimensional (3D) branchline coupler. A second through silicon via of the plurality of through silicon vias forms a second port of the 3D branchline coupler. A third through silicon via of the plurality of through silicon vias forms a third port of the 3D branchline coupler. A fourth through silicon via of the plurality of through silicon vias forms a fourth port of the 3D branchline coupler.

3D-microstrip branchline coupler

A vertical three dimensional (3D) microstrip line structure for improved tunable characteristic impedance, methods of manufacturing the same and design structures are provided. More specifically, a method is provided that includes forming a first microstrip line structure within a back end of the line (BEOL) stack. The method further includes forming a second microstrip line structure separated from the BEOL stack by a predetermined horizontal distance.

On-chip vertical three dimensional microstrip line with characteristic impedance tuning technique and design structures

A high performance on-chip vertical coaxial cable structure, method of manufacturing and design structure thereof is provided. The coaxial cable structure includes an inner conductor and an insulating material that coaxially surrounds the inner conductor. The structure further includes an outer conductor which surrounds the insulating material. Both the inner and outer conductors comprise a plurality of metal layers formed on different wiring levels and interconnected between the different wiring levels by conductors. The coaxial cable structure is formed upon a surface of a semiconductor substrate and is oriented in substantially perpendicular alignment with the surface.

High performance on-chip vertical coaxial cable, method of manufacture and design structure

A three dimensional (3D) branchline coupler using through silicon vias (TSV), methods of manufacturing the same and design structures are disclosed. The method includes forming a first waveguide structure in a first dielectric material. The method further includes forming a second waveguide structure in a second dielectric material. The method further includes forming through silicon vias through a substrate formed between the first dielectric material and the second dielectric material, which connects the first waveguide structure to the second waveguide structure.

Three dimensional branchline coupler using through silicon vias and design structures

On-chip, high performance, slow-wave coplanar waveguide with through-silicon via structures, method of manufacture and design structures for integrated circuits are provided herein. The method includes forming at least one ground plane layer in a substrate and forming a signal layer in the substrate, in a same plane layer as the at least one ground. The method further includes forming at least one metal filled through-silicon via between the at least one ground plane layer and the signal layer.

On-chip slow-wave through-silicon via coplanar waveguide structures, method of manufacture and design structure

A methodology for developing metal fill as a library device and, in particular, a method of generating a model of the effects (e.g., capacitance) of metal fills in an integrated circuit and a design structure is disclosed. The method is implemented on a computing device and includes generating a model for effects of metal fill in an integrated circuit. The metal fill model is generated prior to completion of a layout design for the integrated circuit.

Methodology on developing metal fill as library device

An on-chip tunable transmission line (t-line), methods of manufacture and design structures are provided. The structure includes a tunable transmission line (t-line) with fixed characteristic impedance comprising functionally-differentiated switches used for inductance and capacitance, respectively.

Growing community of inventors

South Burlington, VT, United States of America

Guoan Wang