Infineon Technologies Ag

Infineon Technologies North America Corp.

Other

Gunther Lehmann

Gerd Frankowsky

Siddharth Gupta

Yannick Martelloni

Jean-Yves Larguier

Louis L Hsu

Ulrich Frey

Franz Ungar

Christian Cornelius Russ

Henning Haffner

Devesh Dwivedi

Gabriel Daniel

Vianney Antoine Choserot

Thomas Boehler

Armin M Reith

Steffen Schumann

Prashant Chaudhry

Frederic Gueganton

Gurushiddappa Naduvinamane

David R Hanson

Wolfgang Hokenmaier

Norman Whitelaw Robson

Axel Christoph Brintzinger

Hartmud Terletzki

Manfred Menke

Mario Di Ronza

Oliver Weinfurtner

Gupta Siddharth

Michael Diel

Siddarth Gupta

Matthias Knopf

Stephan Kraus

Juei Lung Chen

Tina Leidinger

Christoph Brintzinger

In accordance with an embodiment, a memory cell device includes at least one memory cell; a first switch connected between the at least one memory cell and a reference potential node; a second switch connected between the at least one memory cell and the reference potential node, and switch driver logic adapted to put the first switch selectively into one of at least three operating states by activation or deactivation of a first subcircuit of the switch driver logic, wherein the at least three operating states comprises an on state, an off state, and a conductive state in which an electrical conductivity of the first switch is lower than in the on state and higher than in the off state, and put the second switch selectively into one of the at least three operating states by activation or deactivation of a second subcircuit of the switch driver logic.

Memory cell device and method for operating a memory cell device

According to one embodiment, a memory device is described including a memory array including a plurality of memory cells wherein each memory cell is coupled to a control line, a memory assist circuit configured to, when activated, apply a reduction of a voltage of the control line, a signal generator configured to generate a signal representing at least one of a process corner of the memory device, a supply voltage of the memory device, a temperature of the memory device and an aging of the memory device, a signal processing circuit configured to amplify the signal and a controller configured to activate the memory assist circuit based the amplified signal.

Memory device and methods for controlling a memory assist function

An electrical device with a fin structure, a first section of the fin structure having a first width and a first height, a second section of the fin structure having a second width and a second height, wherein the first width is smaller than the second width and the first height is lower than the second height.

Electrical device and fabrication method

Methods and devices are disclosed where a voltage on a wordline is changed from a first voltage to a second voltage via a plurality of intermediate voltages.

Wordline activation

Implementations are presented herein that relate to a fuse device, an integrated circuit including a fuse device, a method of implementing a fuse device and a method of programming a fuse device.

Fuse device

A read-out circuit for or in a ROM memory, comprises an input, a comparator circuit, a threshold setting, and a control signal generator for driving the threshold setting generator. A read signal can be coupled into the input. The read signal, depending on the information contained in the read signal, comprises a high signal level relative to a reference potential or a low signal level relative to a reference potential. The comparator circuit compares the read signal with a settable threshold, the threshold setting circuit is designed for setting the threshold of the comparator circuit relative to the high and low signal levels, and the control signal generator generates a control signal similar to the read signal.

Read-out circuit for or in a ROM memory; ROM memory and method for reading the ROM memory

Embodiments of the invention provide a memory device comprising a non-volatile memory element, a read-out circuit for reading out an item of memory information stored in the memory element, a switching unit, by means of which a supply voltage can be applied to the read-out circuit, and a control unit, which has the capability of controlling the switching unit in a manner dependent on the memory information stored in the memory element.

Non-volatile memory device with controlled application of supply voltage

The invention relates to a ROM memory cell comprising a first terminal connected to a word line, comprising a second terminal and comprising a third terminal, the second terminal being connected to a bit line and/or the third terminal being connected to a supply line for precharging the third terminal. The ROM memory cell according to the invention is distinguished by the fact that the same reference potential is in each case applied to the first terminal, the second terminal and/or the third terminal in a standby operating mode. The invention furthermore relates to a ROM memory component comprising such ROM memory cells, and to a method for reading from the ROM memory cell.

ROM memory component featuring reduced leakage current, and method for writing the same

A memory device has a first core memory array, a second core memory array, a third core memory array and a fourth core memory array, and a first common reference section for the first core memory array and the second core memory array, and a second common reference section for the third core memory array and the fourth core memory array. Another memory device with shared signals and a method is also provided.

Memory device with shared reference and method

A method supplies voltage to a bit line of a memory device. The method includes precharging, with a precharging device, the bit line to an output potential, deactivating the precharging device during a read action related to the bit line, reading, during the read action, an information via the bit line, and routing, during the read action, a virtual voltage supply line to a supply potential of the memory device to supply voltage to memory cells of the memory device assigned to the bit line. The precharging device of the bit line is activated/deactivated as a function of the potential of the virtual voltage supply line.

Supplying voltage to a bit line of a memory device

A read-out circuit is disclosed, where the circuit reads information out of a memory unit comprising two non-volatile memory cells. The cells have different programming states, and the memory information of the memory unit is given by the programming states of the two memory cells. The read-out circuit has a volatile signal memory, the inputs of which are connected to the read outputs of the memory cells.

Differential read-out circuit for fuse memory cells

A memory device is provided, the memory device having a memory cell, a programming unit for programming the memory cell, and a switching unit for optionally connecting or isolating a terminal of the memory cell to or from a potential which serves for altering an electrical property of the memory cell and for thereby effecting an altered programming state of the memory cell.

Fuse memory cell with improved protection against unauthorized access

It is proposed that bitline inversion coding data be integrally stored in the structure of a column multiplexer of a storage device. For this purpose, connections to a predefined potential are selectively provided at connection points, which are respectively assigned to one of the bitlines connected to the column multiplexer, in dependence on whether or not the assignment of a first state and of a second state of memory cells, connected to the bitline, to a binary value '0' and to a binary value '1' is inverted for the respective bitline. The connection points are connected to a common nodal point via switching means. The switching means are activated through control signals of the column multiplexer. Selection signals for activating inverter means, in order to effect a selective inversion of values read out from the memory cells, are generated in dependence on the signal level at the common nodal point. A precharging of the common nodal point is preferably effected between to read-out operations in each case, for which purpose precharging switching means are provided.

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Poughkeepsie, NY, United States of America

Gunther Lehmann