Samsung Electronics Co., Ltd.

Gunho Jo

Byounghak Hong

Kang-Ill Seo

Ki-Il Kim

Kang-ill Seo

Seunghyun Song

Inchan Hwang

Daewon Ha

Harsono S Simka

Seungchan Yun

Jeonghyuk Yim

Rebecca Park

Sooyoung Park

Wonhyuk Hong

Ming He

Hyoeun Park

Myunghoon Jung

JaeHyun Park

WookHyun Kwon

Mehdi Saremi

Ki-il Kim

Integrated circuit devices including a bipolar junction transistor (BJT) and/or a P-N junction diode are provided. The integrated circuit devices may include a first stack including first and second semiconductor regions that are spaced apart from each other in a horizontal direction and have a first conductivity type and a plurality of nano-semiconductor layers that are stacked in a vertical direction and are between the first and second semiconductor regions. The plurality of nano-semiconductor layers each have a second conductivity type, and the first semiconductor region may include a side surface facing the plurality of nano-semiconductor layers. The integrated circuit device may also include a vertical semiconductor layer having the second conductivity type and a conductive contact that contacts the plurality of nano-semiconductor layers. The vertical semiconductor layer may contact the side surface of the first semiconductor region and the plurality of nano-semiconductor layers.

Bipolar junction transistors and P-N junction diodes including stacked nano-semiconductor layers

Methods of forming an integrated circuit devices may include providing first and second active regions, an isolation layer, and first and second sacrificial stack structures. The first and second sacrificial stack structures may contact the first and second active regions, and the first and second sacrificial stack structures may each include a channel layer and a sacrificial layer. The methods may also include forming an etch stop layer on the isolation layer, replacing portions of the first and second sacrificial stack structures with first and second source/drain regions, forming a front contact including a front contact plug, forming a back-side insulator, and forming a back contact plug in the isolation layer and the back-side insulator. At least one of a portion of the front contact plug and a portion of the back contact plug may be in the etch stop layer.

Integrated circuit devices including backside power rail and methods of forming the same

Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

Stacked transistors having an isolation region therebetween and a common gate electrode, and related fabrication methods

Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

Devices including stacked nanosheet transistors

Methods of forming a plurality of transistor stacks are provided. A method of forming a plurality of transistor stacks includes etching a plurality of nanosheets, using a plurality of spacers that are on sidewalls of a plurality of semiconductor fins as an etch mask, to provide a plurality of spaced-apart nanosheet stacks that each have at least one of the semiconductor fins thereon.

Methods of forming fin-on-nanosheet transistor stacks

A multi-stack semiconductor device includes: a substrate; and a plurality of multi-stack transistor structures arranged on the substrate in a channel width direction, wherein the multi-stack transistor structure include at least one lower transistor structure and at least one upper transistor structure stacked above the lower transistor structure, wherein the lower and upper transistor structures include at least one channel layer as a current channel, wherein the lower transistor structures of at least two multi-stack transistor structures have different channel-layer widths.

Size-controllable multi-stack semiconductor device and method of manufacturing the same

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Clifton Park, NY, United States of America

Gunho Jo