Stmicroelectronics S.r.l.

Consiglio Nazionale Delle Ricerche

Guglielmo Fortunato

Luigi Mariucci

Angelo Magri′

Cateno Marco Camalleri

Dario Salinas

Massimo Cuscuna

Salvatore Leonardi

Salvatore Coffa

Claudia Caligiore

Massimo Cuscuna′

A process for manufacturing a MOS device and the MOS device manufactured thereby are disclosed. The process includes in a semiconductor layer forming a gate structure above the semiconductor layer; forming a first doped region within a first surface portion of the semiconductor layer; and irradiating the first doped region with electromagnetic radiation, to carry out annealing thereof. Prior to the irradiating step, a dielectric mirror is formed above a second surface portion of the semiconductor layer. The dielectric mirror, which may be of the Bragg-reflector type, reflects at least in part the electromagnetic radiation, and protects underlying regions from the electromagnetic radiation.

Process for manufacturing a large-scale integration MOS device and corresponding MOS device

A process for realizing TFT devices on a substrate comprises the steps of: forming on the substrate, in cascade, an amorphous silicon layer and a heavily doped amorphous silicon layer, forming a photolithographic mask on the heavily doped amorphous silicon layer provided with an opening, removing the heavily doped amorphous silicon layer through the opening for realizing opposite portions of the heavily doped amorphous silicon layer whose cross dimensions decrease as long as they depart from the amorphous silicon layer, removing the photolithographic mask, carrying out a diffusion and activation step of the dopant contained in the portions of the heavily doped amorphous silicon layer inside the amorphous silicon layer, for realizing source/drain regions of said TFT device.

Process for manufacturing a TFT device with source and drain regions having gradual dopant profile

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Rome, Italy

Guglielmo Fortunato