Infineon Technologies Ag

Infineon Technologies LLC

Guenter Gerstmeier

Michael Maldei

Steven Michael Baker

Jon Stanley Berry, Ii

Brian Cousineau

Jinhwan Lee

Thoai-Thai Le

Malati Hedge

George William Alexander

David SuitWai Ma

Tao Wang

Juergen Lindolf

Georg Antonischki

Daivid SuitWai Ma

Malati Hegde

Jinwhan Lee

Wenchao Zheng

Shane Sanders

Marco Ziegelmaier

A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.

High density DRAM with reduced peripheral device area and method of manufacture

A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process includes depositing a middle-of-line liner using plasma enhanced chemical vapor deposition overlying the semiconductor structure. By using a plasma enhanced chemical vapor deposition the amount of MOL liner deposited in the core region and the periphery region can be controlled depending on the distances between transistors in the core region and periphery region.

Maskless middle-of-line liner deposition

An integrated circuit having a signal bus carrying address signals includes mode selection means. The mode selection means has a default state and a non-default state. The integrated circuit is placed into a default and generic mode of operation when the mode selection means is in the default state. An address signal applied to the integrated circuit is interpreted as a specific mode of operation when the integrated circuit is in the default and generic mode of operation. The mode selection means when in the non-default state precludes placement of the integrated circuit into the default and generic mode of operation.

Method and apparatus for placing an integrated circuit into a default mode of operation

A self-alignment system for complement clock signals includes a first delay circuit and a second delay circuit. A first clock signal may be propagated through the first delay circuit and a second clock signal may be propagated through the second delay circuit. A propagation delay of each of the first and second delay circuits may be selectively varied as a function of the first and second clock signals.

Self alignment system for complement clocks

A dynamic random access memory (DRAM) structure having a distance less than 0.14 &#x3bc;m between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.

A DRAM memory unit contains a memory bit (mbit) transistor and a capacitive region for storing charge. The memory is configured to store data as a charge stored by the capacitive region. Each memory unit is accessed by an associated wordline and the data stored by the memory unit is read from an associated bitline connected to the memory unit. The memory units are connected to the associated wordline via a wordline contact and connected to the associated bitline via a bitline contact. The memory units are arranged in memory unit clusters that include multiple memory units having a common bitline contact. The wordline contact is configured to provide for orientation of the wordlines in the memory array independent of the orientation of the bitlines. The wordline contact is also configured to provide for at least one wordline layer separated from the memory unit by a height of the wordline contact. The wordline contact may be further configured to provide an upper wordline layer and a lower wordline layer each being above the bitline relative to the memory unit.

Wordline gate contact for an MBIT transistor array layout

A method of adjusting a control signal that includes generating a control signal at an unknown frequency and automatically adjusting the unknown frequency of the control signal based on the unknown frequency.

Auto-adjustment of self-refresh frequency

A capacitor for a semiconductor device and a method of manufacturing a capacitor for a semiconductor device is disclosed that uses radial current flow. The capacitor includes a semiconductor substrate that includes a plurality of insulation islands. An insulation layer is formed over the semiconductor substrate. Gate electrodes are formed on top of the insulation layer. An array of CD contact pads including a plurality of CD contacts are connected to the semiconductor substrate in a first predetermined number of locations. An array of CG contact pads including at least one CG contact connected to the gate electrodes such that each CG contact is connected to a respective gate electrode above a respective insulation island in a second predetermined number of locations.

Microelectronic capacitor structure with radial current flow

A cooling hood for a circuit board is provided. The circuit board includes at least one semiconductor device. The cooling hood includes a duct mounted onto the circuit board and surrounding at least a portion of the semiconductor device. The duct forms an inlet and an outlet. A cooling medium enters the duct through the inlet and exits the duct through the outlet.

Growing community of inventors

Chapel Hill, NC, United States of America

Guenter Gerstmeier