Csmc Technologies Fab2 Co., Ltd.

Csmc Technologies Fab1 Co., Ltd.

Guangyang Wang

Zhongyu Lin

Meng Dai

Yonghai Hu

Guipeng Sun

Jun Sun

A semiconductor device includes a semiconductor substrate, a field oxide layer, a gate region and field plate integrated structure and a plurality of contact holes. A body region and a drift region are formed in the semiconductor substrate. An active region is formed in the body region, and a drain region is formed in the drift region. A field oxide layer is located on the drift region and the drift region surrounds a part of the field oxide layer. An integrated structure including a gate region and a field plate, the integrated structure extending from above the field oxide layer to above the body region. A depth of a contact hole closer to the source region penetrating into the field oxide layer is greater than a depth of a contact hole closer to the drain region penetrating into the field oxide layer.

Semiconductor device

A semiconductor device for enhancing electrostatic discharge (ESD) protection and a layout structure thereof are provided. An ESD protection device and a protected device () with a small feature linewidth are located on the same well region. The device () with the small feature linewidth is located at a middle portion. The ESD protection device is disposed at both sides of the device () with the small feature linewidth.

Semiconductor device for enhancing electrostatic discharge protection and layout structure thereof

An electrostatic protection device of an LDMOS silicon controlled structure comprises a P-type substrate (), an N-well () and a P-well () on the substrate, a gate electrode () overlapping on the P-well () and extending to an edge of the N-well (), a first N+ structure and a first P+ structure provided in the N-well (), and a second N+ structure and a second P+ structure provided in the P-well (), the first N+ structure being a drain electrode N+ structure (), the first N+ structure being a drain electrode N+ structure (), the first P+ structure being a drain electrode P+ structure (), the second N+ structure being a source electrode N+ structure (), the second P+ structure being a source P+ structure (), and a distance from the drain electrode P+ structure () to the gate electrode () being greater than a distance from the drain electrode N+ structure () to the gate electrode ().

Electrostatic protection device of LDMOS silicon controlled structure

An electrostatic discharge protection structure includes: substrate of a first type of conductivity, well region of a second type of conductivity, substrate contact region in the substrate and of the first type of conductivity, well contact region in the well region and of the second type of conductivity, substrate counter-doped region between the substrate contact region and the well contact region and of the second type of conductivity, well counter-doped region between the substrate contact region and the well contact region and of the first type of conductivity, communication region at a lateral junction between the substrate and the well region, first isolation region between the substrate counter-doped region and the communication region, second isolation region between the well counter-doped region and the communication region, oxide layer having one end on the first isolation region and another end on the substrate, and field plate structure on the oxide layer.

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Jiangsu, China

Guangyang Wang