Csmc Technologies Fab2 Co., Ltd.

Csmc Technologies Fab1 Co., Ltd.

Guangsheng Zhang

Sen Zhang

Guipeng Sun

Shukun Qi

Nailong He

Yun Lan

A manufacturing method of an LDMOS device comprises: obtaining a wafer formed with a doped region having a first conductivity type, wherein a top buried layer is formed inside the doped region having the first conductivity type, and a field oxide insulation layer structure is formed on the top buried layer; disposing a trench on the doped region having the first conductivity type, wherein the trench extends to the top buried layer and the field oxide insulation layer structure such that a portion of the top buried layer is removed; injecting an ion of a second conductivity type to form a well region below the trench; and forming a doped source region in the well region. The first conductivity type and the second conductivity type are opposite conductivity types.

Method of manufacturing an LDMOS device having a well region below a groove

A semiconductor device includes a substrate (); a buried layer () formed on the substrate (), a diffusion layer () formed on the buried layer (), wherein the diffusion layer () includes a first diffusion region () and a second diffusion region (), and an impurity type of the second diffusion region () is opposite to an impurity type of the first diffusion region (); the diffusion layer () further comprises a plurality of third diffusion regions () formed in the second diffusion region, wherein an impurity type of the third diffusion region () is opposite to the impurity type of the second diffusion region (); and a gate () formed on the diffusion layer ().

Semiconductor device and related method of adjusting threshold voltage in semiconductor device during manufacture via counter doping in diffusion region

Provided is a laterally diffused metal-oxide-semiconductor field-effect transistor, comprising a substrate (), a source (), a drain (), a body region (), a P-type field-limiting ring (), and a well region on the substrate (); the well region comprises an inserted well (), which has P-type doping and is disposed below the drain and connected to the drain; N wells () disposed at the two sides of the inserted well (); a P well () disposed next to the N well () and connected to the N well (); a P-type field-limiting ring (), which is disposed inside the N well (), is a closed ring-shaped structure, and is located at the periphery below the drain (); the inserted well () extends in its longitudinal direction to the position where it is in contact with said P-type field-limiting ring (); the source () and the body region () are disposed inside the P well ().

Laterally diffused metal-oxide-semiconductor field-effect transistor

The present disclosure relates to a semiconductor device with an ESD protection structure. The semiconductor device includes a high-voltage power device, the ESD protection structure is a NMOS transistor, a drain of the NMOS transistor is shared by a source of the power device as a common-drain-source structure, substrate leading-out regions of the power deviceand the NMOS transistor are coupled to the sourceof the NMOS transistor as a ground leading-out. In the present disclosure, the drain of the NMOS transistor is shared by the source of the power device, so the increased area of the device with the ESD protection structure incorporated is small. In addition, the holding voltage at the source of the high-voltage power device is relatively low, which helps to protect the gate oxide and improve the source reliability.

Semiconductor device having ESD protection structure

A laterally diffused metal oxide semiconductor device includes: a substrate (); a buried layer region () in the substrate; a well region () on the buried layer region (); a gate region on the well region; a source region () and a drain region () which are located at two sides of the gate region; and a super junction structure. The source region () is located in the well region (); the drain region () is located in the super junction structure; the gate region comprises a gate oxide layer and a gate electrode on the gate oxide layer; and the super junction structure comprises a plurality of N-columns and P-columns, wherein the N-columns and the P-columns are alternately arranged in a direction which is horizontal and is perpendicular to the direction of a connecting line between the source region and the drain region, each N-column comprises a top-layer N-region () and a bottom-layer N-region which are butted vertically, and each P-column comprises a top-layer P-region () and a bottom-layer P-region which are butted vertically.

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Wuxi New District, China

Guangsheng Zhang