Efficient Power Conversion Corporation

Guang Yuan Zhao

Robert A Beach

Jianjun Cao

Alexander Lidow

Alana Nakata

Robert Strittmatter

Johan Tjeerd Strydom

Fang Chang Liu

Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.

Semiconductor devices with back surface isolation

An enhancement mode GaN transistor having a gate pGaN structure having a thickness which avoids dielectric failure. In one embodiment, this thickness is in the range of 400 &#x212b; to 900 &#x212b;. In a preferred embodiment, the thickness is 600 &#x212b;.

Enhancement mode gallium nitride transistor with improved gate characteristics

A self-aligned transistor gate structure that includes an ion-implanted portion of gate material surrounded by non-implanted gate material on each side. The gate structure may be formed, for example, by applying a layer of GaN material over an AlGaN barrier layer and implanting a portion of the GaN layer to create the gate structure that is laterally surrounded by the GaN layer.

Ion implanted and self aligned gate structure for GaN transistors

Enhancement-mode GaN devices having a gate spacer, a gate metal material and a gate compound that are self-aligned, and a methods of forming the same. The materials are patterned and etched using a single photo mask, which reduces manufacturing costs. An interface of the gate spacer and the gate compound has lower leakage than the interface of a dielectric film and the gate compound, thereby reducing gate leakage. In addition, an ohmic contact metal layer is used as a field plate to relieve the electric field at a doped III-V gate compound corner towards the drain contact, which leads to lower gate leakage current and improved gate reliability.

Enhancement mode GaN HEMT device with gate spacer and method for fabricating the same

An enhancement-mode GaN transistor, the transistor having a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate containing acceptor type dopant elements, and a diffusion barrier comprised of a III Nitride material between the gate and the buffer layer.

Back diffusion suppression structures

An enhancement mode gallium nitride (GaN) transistor with a Mg doped layer and a Mg growth interruption (diffusion barrier) layer to trap excess or residual Mg dopant. The Mg growth interruption (diffusion barrier) layer is formed by growing GaN, stopping the supply of gallium while maintaining a supply of ammonia or other nitrogen containing source to form a layer of magnesium nitride (MgN), and then resuming the flow of gallium to form a GaN layer to seal in the layer of MgN.

Dopant diffusion modulation in GaN buffer layers

An enhancement-mode GaN transistor and a method of forming it. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.

Enhancement mode GaN HEMT device and method for fabricating the same

A MISFET, such as a GaN transistor, with low gate leakage. In one embodiment, the gate leakage is reduced with a compensated GaN layer below the gate contact and above the barrier layer. In another embodiment, the gate leakage is reduced by employing a semi-insulating layer below the gate contact and above the barrier layer.

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Torrance, CA, United States of America

Guang Yuan Zhao