Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Au Optronics Corporation

Tsinghua University

Guan-Yu Chen

Tin-Hao Kuo

Chen-Shien Chen

Yu-Wei Lin

Yi-Ping Lin

Jung-Yu Li

Shih-Pu Chen

Jin-Han Wu

Cheng-Chang Chen

Cheng-Hung Li

Chen-Hua Douglas Yu

Yu-min Liang

Yu-Jen Tseng

Hao-Yi Tsai

Der-Chyang Yeh

An-Jhih Su

Han-Ping Pu

Chih-Hao Chang

Li-Hsien Huang

Yu-Feng Chen

Meng-Tse Chen

Tsung-Hsien Chiang

Yi-Feng Chang

Ming-Shih Yeh

Wei Sen Chang

Yu-Chen Hsu

Ming-Fang Lai

Mirng-Ji Lii

Yen-Liang Lin

Sheng-Yu Wu

Chao-Wei Li

Syuan-Ling Yang

Wei-Ming Cheng

Min-Hsuan Chiu

Yu-Chen Hu

Wen-Yang Hsu

Hsing-Yu Tuan

Huei-Jhen Siao

The present invention provides a polarizer module and an operation method thereof. The polarizer module includes a bifacial reflective polarizer, a first liquid crystal layer, a second liquid crystal layer, a first polarizer, and a second polarizer. The bifacial reflective polarizer has a first surface and a second surface opposite to each other. The first liquid crystal layer and the second liquid crystal layer are disposed on the first surface and the second surface respectively. The first polarizer and the second polarizer are disposed on the first liquid crystal layer and the second liquid crystal layer respectively.

Polarizer module and operation method thereof

An integrated circuit includes a semiconductor substrate, devices, first tap regions, and second tap regions. The devices are over the semiconductor substrate. The first tap regions are over the semiconductor substrate along a first direction. The second tap regions are over the semiconductor substrate along the first direction. A first pitch between adjacent two of the first tap regions in the first direction is greater than a second pitch between adjacent two of the second tap regions in the first direction.

Integrated circuit having latch-up immunity

A chip package including an integrated circuit component, a thermal conductive layer, an insulating encapsulant and a redistribution circuit structure is provided. The integrated circuit component includes an amorphous semiconductor portion located at a back surface thereof. The thermal conductive layer covers the amorphous semiconductor portion of the integrated circuit component, wherein thermal conductivity of the thermal conductive layer is greater than or substantially equal to 10 W/mK. The insulating encapsulant laterally encapsulates the integrated circuit component and the thermal conductive layer. The redistribution circuit structure is disposed on the insulating encapsulant and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component.

Chip package and method of fabricating the same

A method for forming an integrated circuit (IC) is provided. The method includes obtaining an IC design; generating a layout according to the IC design; calculating a score of a region in the layout based on voltage levels in the region; and fabricating a semiconductor device according to the layout when the score of the region in the layout is equal to or less than a threshold value.

Integrated circuit and method for forming the same

A display apparatus includes a backlight, a first polarizer, a light controlling panel, a second polarizer, a display panel, and a third polarizer sequentially arranged along a direction. A transmission axis of the first polarizer and a transmission axis of the second polarizer are substantially parallel, and the transmission axis of the second polarizer and a transmission axis of the third polarizer are substantially perpendicular. A set of the first polarizer, the light controlling panel, and the second polarizer has a transmittance, and the transmittance has a maximum value when the light controlling panel is not enabled.

Display apparatus

A structure includes a first package component, and a second package component over and bonded to the first package component. A supporting material is disposed in a gap between the first package component and the second package component. A molding material is disposed in the gap and encircling the supporting material.

Pre-applying supporting materials between bonded package components

A light emitting device is disclosed, including a first electrode layer, a second electrode layer, and an organic light emitting layer sandwiched between the first and second electrode layers. The second electrode layer is patterned to form a plurality of electrode patterns arranged with different densities. The organic light emitting layer is subjected to a color separation process to form a plurality of monochromatic blocks that correspond to the electrode patterns, respectively. The electrode patterns are divided into a plurality of electrode pattern groups arranged in an alternate manner. The electrode pattern groups display a same image, and a same voltage is applied to the electrode pattern groups at a same time. Alternatively, the electrode pattern groups display different images, and a same or different voltages are applied to the electrode pattern groups at different times. As such, the light emitting device generates grayscale, full-color, three-dimensional or dynamic images.

Light emitting device free of TFT and chiplet

A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1.

Substrate design with balanced metal and solder resist density

An integrated circuit (IC) packaging substrate includes a main body, at least one first conductive line, at least one second conductive line, and at least one protrusion pad. The first conductive line is embedded in the main body. The second conductive line is embedded in the main body. The protrusion pad is disposed on the first conductive line. The protrusion pad protrudes from the main body and is configured to be in electrical contact with a solder portion of a semiconductor chip. A first spacing between the protrusion pad and the second conductive line is determined in accordance with a process deviation of the protrusion pad by the width of the protrusion pad and the width of the first conductive line. Moreover, a semiconductor package having the IC packaging substrate and a manufacturing method of the semiconductor package are also provided.

Integrated circuit packaging substrate, semiconductor package, and manufacturing method

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

Bump structure and method of forming same

A device package is provided. The device package includes a first die and a second die. A top surface of the first die is offset from a top surface of the second die in a direction that is parallel to a sidewall of the first die. A molding compound extends along sidewalls of the first die and the second die, where at least a portion of a top surface of the molding compound includes an inclined surface. A polymer layer contacts the top surface of the molding compound, the top surface of the first die, and the top surface of the second die. A top surface of the polymer layer is substantially level. A first conductive feature is in the polymer layer, where the first conductive feature is electrically connected to the first die.

Interconnect structures for wafer level package and methods of forming same

The present disclosure provides a method for manufacturing a semiconductor package. The method includes (1) determining a die warpage value under a predetermined temperature range; (2) determining a difference between a density of a top metal and a density of a bottom metal of a substrate according to the die warpage value; and (3) joining the die and the substrate under the predetermined temperature range. The top metal includes all metal layers overlying a middle layer, and the bottom metal includes all metal layers underlying the middle layer. The middle layer includes a core or a metal layer.

Semiconductor package and manufacturing method of the same

A light emitting device includes an electrode layer, a first metal layer, an organic material layer and a second metal layer stacked sequentially. The first metal layer includes a first metal portion and a second metal portion separated from the first metal portion at a first lateral distance, and the first metal portion and the second metal portion have a first period. The organic material layer includes a first emitting region separating the first metal portion and the second metal portion. The first lateral distance and the first period enable a lateral plasma coupling generated between the first metal portion and the second metal portion, such that light generated by the organic material layer at the first emitting region has a gain in a first waveband, or a peak wavelength of the light generated by the first emitting region shifts to the first waveband.

Light emitting device

A light emitting device includes a substrate layer, first and second metal layers sequentially formed on the substrate layer, and an organic material layer formed between the first and second metal layers. The first metal layer has a uniform thickness or has metal portions or further has an open portion exposing a portion of the surface of the substrate layer. The organic material layer includes a hole transport material and an electron transport material in contact with one another. An interaction between the hole transport material and the electron transport material generates exciplexes capable of emitting light having a peak wavelength in a first range, and a coupling is generated between the first and second metal layers. By adjusting the distance between the first and second metal layers or the thickness of the first metal layer, the peak wavelength of the light is shifted to a second range and/or a third range.

Growing community of inventors

Hsinchu, Taiwan

Guan-Yu Chen