Intel Corporation

Gregory Scott Mathews

Dean A Mulla

John Wai Cheong Fu

Edward S Zager

Stuart E Sailer

Jeng-Jye Shaw

James P Kardach

Eugene P Matter

Sung Soo Cho

Cau L Nguyen

Kameswaran Sivamani

Ghassan Khadder

Deepak J Aatresh

David S Vannier

Yahya S Sotoudeh

Shing Wong

Edward Thomas Grochowski

Gary N Hammond

John H Crawford

Steven J Tu

Nhon Toai Quach

Tse-Yu Yeh

Judge K Arora

Gautam B Doshi

Tosaku Nakanishi

Sundari S Mitra

Chih-Hung Chung

Sanjay Jain

John Wai Fu

Ketan S Bhat

Selina Sze Wan Yuen

Jarvis Leung

Sreenivas A Reddy

A method is provided for requesting data from a memory. The method includes issuing a plurality of data requests to a data request port for the memory. The plurality of data requests includes at least two ordered data requests. The method includes determining if an earlier one of the ordered data requests corresponds to a miss in the memory, and converting a later one of the ordered data requests to a prefetch in response to the earlier one of the ordered data requests corresponding to a miss in the memory. An apparatus includes a memory having at least one pipelined port for receiving data requests. The port is adapted to determine whether an earlier ordered one of the data requests corresponds to a miss in the memory. The port converts a later ordered one of the data requests to a prefetch in response to determining that the earlier ordered one of the data requests corresponds to a miss in the memory.

Processing ordered data requests to a memory

A cache controller is intimately associated with a microprocessor CPU on a single chip. The physical address bus is routed directly from the CPU to the cache controller where it is sent to the cache tag directory table. For a cache hit, the cache address is remapped to the proper cache set address. For a cache miss, the cache address is remapped in accordance with the LRU logic to direct the cache write to the least recently used set. The cache is thereby functionally divided into associative sets, but without the need to physically divide the cache into independent banks of SRAM.

Single bank associative cache

An apparatus and method to provide ordering when an advanced load address table is used for advanced loads. An advanced load address table (ALAT) is used to retain an entry associated with a location accessed by an advanced load instruction. The entry is utilized to determine if an intervening access to the location is performed by another instruction prior to the execution of a corresponding checking instruction. Ordering is maintained to ensure validity of the entry in the ALAT, when the advanced load instruction is boosted past an ordering setting boundary.

Method and apparatus to provide advanced load ordering

An apparatus and method for reducing power consumption in a processor front end are provided. The processor includes an instruction cache, a TLB, and a branch predictor. For sequential code execution, the instruction cache is disabled unless the next instruction fetch will cross a cache line boundary, thus reducing unnecessary accesses to the instruction cache. The TLB is disabled unless the next instruction fetch will cross a page boundary, thus reducing unnecessary TLB look-ups. For code branching, the branch predictor is configured to include, for each target address, an indication of whether the target address is in the same page as the corresponding branch address. When a branch occurs so as to cause access to a given entry in the branch predictor, the TLB is disabled if the target address is in the same page as the branch address.

Apparatus and method for reducing power consumption due to cache and TLB accesses in a processor front-end

A computer product, method, and apparatus for causing a computer to perform load operations in a particular way are disclosed. The computer is made to replace a load instruction at a particular location in a computer program instruction sequence with two instructions, an advanced load instruction and a load check instruction. The advanced load instruction is inserted into the instruction sequence up-stream from where the original load instruction was located, and may be inserted above store instructions. The load check instruction is inserted into the instruction sequence after the store instructions. An Advanced Load Address Table (ALAT) structure, containing physical address data and validity data for each non-speculative advanced load, is updated with data about each advanced load and each store instruction executed, and queried on execution of each load check instruction about whether or not a particular advanced load is safe to use. An advanced load speculative pipeline and speculative invalidation pipeline are similarly queried regarding speculative advanced loads.

Method and apparatus for advancing load operations

A translation buffer is described which can translate virtual addresses to physical addresses wherein the virtual addresses have varying page sizes. The translation buffer includes a decoder to generate a hashed index, the index identifying an entry into two arrays. The first of the two arrays identifies a corresponding physical page address and the other array identifies a corresponding variable page address that in comparison to a variable portion of the virtual address, will indicate whether the entry in the first array has a matching entry. If the first array identifies a matching physical page address, then the physical page address is combined with the offset of the virtual address to yield a physical address translation of the virtual address.

System and method for translation buffer accommodating multiple page sizes

An apparatus includes a plurality of error detection circuits. Each of the plurality of error detection circuits is coupled to one of a like plurality of ways in a set associative cache memory to receive a tag word and an error detection flag from the coupled way. Each of the plurality of error detection circuits generates a way error signal that is asserted if an error is detected in the tag word of the coupled way. A logical OR circuit is coupled to the plurality of error detection circuits to receive the plurality of way error signals. The logical OR circuit generates a tag error signal that is asserted if at least one of the plurality of way error signals is asserted.

Method and apparatus for set associative cache tag error detection

A prevalidation content addressable memory, CAM, is used to pre-decode a virtual address region extension and enable it for use by a translation look-aside buffer, TLB. The prevalidation CAM removes the region extensions stored in region registers from a serial TLB look-up path.

TLB using region ID prevalidation

A method is provided for managing temporal and non-temporal data in the same cache structure. The temporal or non-temporal character of data targeted by a cache access is determined, and a cache entry for the data is identified. When the targeted data is temporal, a replacement priority indicator associated with the identified cache entry is updated to reflect the access. When the targeted data is non temporal, the replacement priority indicator associated with the identified cache entry is preserved. The method may also be implemented by employing a first algorithm to update the replacement priority indicator for temporal data and a second, different algorithm to update the replacement priority indicator for non-temporal data.

Method and apparatus for managing temporal and non-temporal data in a single cache structure

A novel on-chip cache memory and method of operation are provided which increase microprocessor performance. The cache design allows two cache requests to be processed simultaneously (dual-ported) and concurrent cache requests to be in-flight (pipelined). The design of the cache allocates a first clock cycle to cache tag and data access and a second cycle is allocated to data manipulation. The memory array circuit design is simplified because the circuits are synchronized to the main processor clock and do not need to use self-timed circuits. The overall logic control scheme is simplified because distinct cycles are allocated to the cache functions.

High performance fully dual-ported, pipelined cache design

A fully-associative translation lookaside buffer structure for a computer system includes a first-level TLB memory having a plurality of entries and a second-level TLB memory operatively coupled to the first level TLB memory. The second-level TLB memory also has a plurality of entries. Entries are placed in the TLB and TLB structure as a result of software controlled translation register operations and hardware controlled translation cache operations. Logic controlling TLB treats both operations the same way and uses a hardware replacement algorithm to determine the entry index. Logic controlling TLB uses a hardware replacement algorithm to determine the entry index for translation cache entries, and use an index provided within the insertion instruction to determine the entry index for translation register operations.

Hierarchical fully-associative-translation lookaside buffer structure

A technique for receiving a first data from a storage location in which the first data is not stored fully aligned within processor data boundaries for data retrieval. The adder also receives a second data having its alignment adjusted to correspond to the first data and adds the first data and the second data in CPU unaligned format. A carry control circuit coupled to the adder determines which carries are selected for transfer to the next stage for calculating a sum of the two data.

Unaligned semaphore adder

A decentralized exception processing system includes a plurality of local exception units. Each local exception unit is coupled to process local exception signals from one or more processing resources that are proximate to it. Each local exception unit generates local commit signals, using order information for the instruction in an issue group and any local exception signals it receives. The local commit signals are combined to generate a global commit signal for each instruction in the issue group. Local exception signals are collected at a selected one of the local exception units and processed to generate a global exception unit. The selected local exception unit resteers control of the processing resources to an exception handler associated with the global exception unit.

Decentralized exception processing system

A cache controller is associated with a microprocessor CPU on a single chip. The physical address bus is routed directly from the CPU to the cache controller where addresses are compared with entries in the cache tag directory table. For a cache hit, the cache address is remapped to the proper cache set address. For a cache miss, the cache address is remapped in accordance with the LRU logic to direct the cache write to the least recently used set. The cache is thereby functionally divided into associative sets, but without the need to physically divide the cache into independent banks of SRAM.

Growing community of inventors

Santa Clara, CA, United States of America

Gregory Scott Mathews