Freescale Semiconductor,inc.

Gregory S Spencer

Mariam G Sadaka

Robert E Jones

Kurt H Junker

Gauri V Karve

Voon-Yew Thean

Tab Allen Stephens

Vishal P Trivedi

Dina H Triyoso

Peter J Beckage

Dean J Denning

Victor H Vartanian

Marc A Rossow

Jill C Hildreth

Gerald A Martin

Debby Eades

Bich-Yen Nguyen

Ted R White

Michael D Turner

Paul Grudowski

Venkat Kolagunta

John M Grant

Stefan Zollner

Veeraraghavan Dhandapani

Phillip E Crabtree

Narayanan C Ramani

Melissa O Zavala

Joe Mogab

Veer Dhandapani

Philip E Crabtree

Jason A Vires

A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.

Method of making a die with recessed aluminum die pads

A semiconductor structure having a transistor region and an optical device region includes a transistor in a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer. A gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and the transistor is formed in the transistor region of the semiconductor structure. A waveguide device in the optical device region and a third semiconductor layer over a portion of the second semiconductor layer.

Semiconductor device with photonics

A method for forming a semiconductor structure having a transistor region and an optical device region includes forming a transistor in and on a first semiconductor layer of the semiconductor structure, wherein the first semiconductor layer is over a first insulating layer, the first insulating layer is over a second semiconductor layer, and the second semiconductor layer is over a second insulating layer, wherein a gate dielectric of the transistor is in physical contact with a top surface of the first semiconductor layer, and wherein the transistor is formed in the transistor region of the semiconductor structure. The method also includes forming a waveguide device in the optical device region, wherein forming the waveguide device includes exposing a portion of the second semiconductor layer in the optical device region; and epitaxially growing a third semiconductor layer over the exposed portion of the second semiconductor layer.

A semiconductor device is provided which comprises a semiconductor layer (), a dielectric layer (), first and second gate electrodes () having first and second respective work functions associated therewith, and a layer of hafnium oxide () disposed between said dielectric layer and said first and second gate electrodes.

Semiconductor device with selectively modulated gate work function

A method includes forming a first opening in a top surface of a semiconductor substrate, performing an implant into the top surface to form a doped region, epitaxially growing a semiconductor layer in the first opening along a bottom of the first opening and along sidewalls of the first opening, wherein the epitaxially growing comprises in-situ doping the semiconductor layer, filling the first opening with a dielectric material, forming a second opening in the dielectric material, wherein a bottom of the second opening exposes the epitaxially grown semiconductor layer and sidewalls of the second opening expose the dielectric material; and filling the second opening with a semiconductor material, wherein the semiconductor material comprises a top electrode and a bottom electrode. The bottom electrode is in electrical contact with the semiconductor layer which is in electrical contact with the doped region. The doped region is laterally adjacent the semiconductor material.

Method of making a vertical photodetector

A method of forming a doped region includes, in one embodiment, implanting a dopant into a region in a semiconductor substrate, recrystallizing the region by performing a first millisecond anneal, wherein the first millisecond anneal has a first temperature and a first dwell time, and activating the region using as second millisecond anneal after recrystallizing the region, wherein the second millisecond anneal has a second temperature and a second dwell time. In one embodiment, the first millisecond anneal and the second millisecond anneal use a laser. In one embodiment, the first temperature is the same as the second temperature and the first dwell time is the same as the second dwell time. In another embodiment, the first temperature is different from the second temperature and the first dwell time is different from the second dwell time.

Multiple millisecond anneals for semiconductor device fabrication

A semiconductor process and apparatus provide a planarized hybrid substrate () by thermally oxidizing SOI sidewalls () in a trench opening () to form SOI sidewall oxide spacers () which are trimmed while etching through a buried oxide layer () to expose the underlying bulk substrate () for subsequent epitaxial growth of an epitaxial semiconductor layer (). In this way, SOI sidewall oxide spacers () are formed that prevent epitaxial SOI sidewalls from being formed in the trench opening () during the epitaxial growth step, and that can be readily removed during any subsequent STI etch process

Dual substrate orientation or bulk on SOI integrations using oxidation for silicon epitaxy spacer formation

A semiconductor process and apparatus provide a planarized hybrid substrate () by selectively depositing an epitaxial silicon layer () to fill a trench (), and then blanket depositing silicon to cover the entire wafer with near uniform thickness of crystalline silicon () over the epi silicon layer () and polycrystalline silicon () over the nitride mask layer (). The polysilicon material () added by the two-step process increases the polish rate of subsequent CMP polishing to provide a more uniform polish surface () over the entire wafer surface, regardless of variations in structure widths and device densities. By forming first gate electrodes () over a first SOI layer () using deposited () silicon and forming second gate electrodes () over an epitaxially grown () silicon layer (), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes () having improved hole mobility.

Silicon deposition over dual surface orientation substrates to promote uniform polishing

A semiconductor process and apparatus provides a planarized hybrid substrate () by removing a nitride mask layer () and using an oxide polish stop layer () when an epitaxial semiconductor layer () is being polished for DSO and BOS integrations. To this end, an initial SOI wafer semiconductor stack () is formed which includes one or more oxide polish stop layers () formed between the SOI semiconductor layer () and a nitride mask layer (). The oxide polish stop layer () may be formed by depositing a densified LPCVD layer of TEOS to a thickness of approximately 100-250 Angstroms.

Step height reduction between SOI and EPI for DSO and BOS integration

Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer

A semiconductor process and apparatus provide a high performance CMOS devices () with hybrid or dual substrates by etching a deposited oxide layer () using inverse slope isolation techniques to form tapered isolation regions () and expose underlying semiconductor layers () in a bulk wafer structure prior to epitaxially growing the first and second substrates () having different surface orientations that may be planarized with a single CMP process. By forming first gate electrodes () over a first substrate () that is formed by epitaxially growing (100) silicon and forming second gate electrodes () over a second substrate () that is formed by epitaxially growing (110) silicon, a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes having improved hole mobility.

Inverse slope isolation and dual surface orientation integration

A strained semiconductor layer is achieved by a method for transferring stress from a dielectric layer to a semiconductor layer. The method comprises providing a substrate having a semiconductor layer. A dielectric layer having a stress is formed over the semiconductor layer. A radiation anneal is applied over the dielectric layer of a duration not exceeding 10 milliseconds to cause the stress of the dielectric layer to create a stress in the semiconductor layer. The dielectric layer may then be removed. At least a portion of the stress in the semiconductor layer remains in the semiconductor layer after the dielectric layer is removed. The radiation anneal can be either by using either a laser beam or a flash tool. The radiation anneal can also be used to activate source/drain regions.

Transfer of stress to a layer

An anneal of an epitaxially grown crystalline semiconductor layer comprising a combination of group-IV elements. The layer contains at least one of the group of carbon and tin. The layer of epitaxially grown material is annealed at a temperature substantially in a range of 1,000 to 1,400 degrees Celsius for a period not to exceed 100 milliseconds within 10% of the peak temperature. The anneal is performed for example with a laser anneal or a flash lamp anneal. The limited-time anneal may improve carrier mobility of a transistor.

Anneal of epitaxial layer in a semiconductor device

A semiconductor process and apparatus provide a planarized hybrid substrate () having a more uniform polish surface () by thickening an SOI semiconductor layer () in relation to a previously or subsequently formed epitaxial silicon layer () with a selective silicon deposition process that covers the SOI semiconductor layer () with a crystalline semiconductor layer (). By forming first gate electrodes () over a first SOI substrate () using deposited (100) silicon and forming second gate electrodes () over an epitaxially grown (110) silicon substrate (), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes () having improved hole mobility.

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Pflugerville, TX, United States of America

Gregory S Spencer