Intel Corporation

Gregory S Constable

Nisha Ananthakrishnan

Rahul N Manepalli

Nachiket R Raravikar

Leonel R Arana

Carl L Deppisch

Dingying David Xu

Sriram Srinivasan

Deepak Kulkarni

Linda A Shekhawat

Hong Dong

Youzhi E Xu

Vijay Wakharkar

Nirupama Chakrapani

Shankar Ganapathysubramanian

Janet Feng

Nisha Anathakrishan

Nisha Ananthakrishan

Methods and associated structures of forming a package structure including forming a low melting point solder material on a solder resist opening location of an IHS keep out zone, forming a sealant in a non SRO keep out zone region; attaching the IHS to the sealant, and curing the sealant, wherein a solder joint is formed between the IHS and the low melting point solder material.

Methods of fabricating low melting point solder reinforced sealant and structures formed thereby

Underfill materials for fabricating electronic devices are described. One embodiment includes an underfill composition including an epoxy mixture, an amine hardener component, and a filler. The epoxy mixture may include a first epoxy comprising a bisphenol epoxy, a second epoxy comprising a multifunctional epoxy, and a third epoxy comprising an aliphatic epoxy, the aliphatic epoxy comprising a silicone epoxy. The first, second, and third epoxies each have a different chemical structure. Other embodiments are described and claimed.

Flexible underfill compositions for enhanced reliability

An underfill formulation includes a solvent (), a plurality of amphiphilic block copolymers () in the solvent, and an adhesion promoter () in the solvent. Groups of the plurality of amphiphilic block copolymers form a plurality of micelles () in the solvent, with the micelles including a core () and a shell () surrounding the core, and the adhesion promoter is in the core of at least some of the plurality of micelles.

Underfill formulation and method of increasing an adhesion property of same

A microelectronic package is provided. The microelectronic package includes a semiconductor substrate and a die having a top surface and a bottom surface, wherein the bottom surface of the die is coupled to the semiconductor substrate. The microelectronic package also includes a nanomaterial layer disposed on the top surface of the die.

Microelectronic package with wear resistant coating

Growing community of inventors

Chandler, AZ, United States of America

Gregory S Constable