Trw Limited

Gregory P Chapelle

Stephane Mailleau

Lance M Bodnar

A memory access system maps a block of data between a time stamp and an addressable memory location in a manner which mimics actual transmission slot timing. The system includes a slot time module, a calculation conversion module, and an addressing module The slot time module determines the time stamp for the block of data, and the calculation conversion module generates a preliminary memory location based on the time stamp and a predetermined conversion factor. The predetermined conversion factor has a preliminary component which can be removed by the addressing module such that an addressable memory location is generated. The calculation conversion module has a base conversion module, a padding module, a left-shift module; and a summation module for constructing the conversion factor and applying the conversion factor to the retrieved time stamp.

Time slot data memory storage and access system

An error correction and detection technique provides a correction code for correcting single bit errors as well as detecting but not correcting two adjacent bits in error. A received word, which may contain errors, is multiplied by a parity check matrix to produce a syndrome corresponding to one of first and second mutually exclusive sets of syndromes if the received word contains at least one error, each single bit error in the received bit word corresponding one-to-one with a member of the first of the sets of syndromes and each two bit adjacent error corresponding non-uniquely to a member of the second of the sets of syndromes. A syndrome containing all zeros is produced if the received word contains no errors. One bit data errors in the received word are corrected, two bit errors are reported, and no action is taken if the word contains no errors.

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San Diego, CA, United States of America

Gregory P Chapelle