Intermolecular, Inc.

International Business Machines Corporation

Globalfoundries Inc.

Gregory Nowling

John S Foster

Paul Raymond Besser

John Anthony Fitzsimmons

Stephan Kronholz

Berthold Reimer

Joanna Wasyluk

Sven Metzger

Provided are methods for processing semiconductor substrates or, more specifically, etching silicon containing antireflective coatings (SiARCs) from the substrates while preserving silicon oxides layers disposed on the same substrates. An etching solution including sulfuric acid and hydrofluoric acid may be used for these purposes. In some embodiments, the weight ratio of sulfuric acid to hydrofluoric acid in the etching solution is between about 15:1 and 100:1 (e.g., about 60:1). The temperature of the etching solution may be between about 30&#xb0; C. and 50&#xb0; C. (e.g., about 40&#xb0; C., during etching). It has been found that such processing conditions provide a SiARC etching rate of at least about 50 nanometers per minute and selectivity of SiARC over silicon oxide of greater than about 10:1 or even greater than about 50:1. The same etching solution may be also used to remove photoresist, organic dielectric, and titanium nitride.

Wet etching of silicon containing antireflective coatings

Two-step process sequences uniformly etch both tungsten-based and titanium-based structures on a substrate. A sequence of wet etches using peroxide and heated nitric acid uniformly recesses a metal stack that includes W, TiN, and TiAl. W, TiN and TiC are uniformly recessed by a peroxide etch at &#x2dc;25 C followed by an acid solution with a very small amount of added peroxide at &#x2dc;60 C. TiC is etched without etching trench oxides or other metals in a work-function metal stack by either (1) highly-dilute of ultra-dilute HF at 25-35 C, (2) dilute HCl at 25-60 C, (3) dilute NHOH at 25-60 C, or (4) solution (2) or (3) with small amounts of peroxide. Other metals in the stack may then be plasma-etched without being blocked by TiC residues.

Etching of semiconductor structures that include titanium-based layers

Provided are methods for processing semiconductor substrates having titanium nitride (TiN) structures as well as aluminum (Al) structures and, in some embodiments, other structures, such as silicon germanium (SiGe), tantalum nitride (TaN), hafnium oxide (HfOx), silicon nitride (SiN), and/or silicon oxide (SiO) structures. Etching solutions and processing conditions described herein provide high etching selectivity of titanium nitride relative to these other materials. As such, the titanium nitride structures can be removed (partially or completely) without significant damage to these other structures. In some embodiments, the etching rate of titanium nitride is at least about 200 Angstroms per minute and even at least about 350 Angstroms per minute, while the etching rate of aluminum and/or other materials is less than 15 Angstroms per minute. An etching solution may be kept at 40&#xb0; C. to 65&#xb0; C. and may include ammonium hydroxide and hydrogen peroxide (between 1:600 and 1:3,000 by weight).

Selective etching of titanium nitride

Provided are methods for processing semiconductor substrates. The methods involve etching silicon nitride structures using phosphoric acid solutions maintained at low temperatures, such as between about 110&#xb0; C. and 130&#xb0; C. These temperatures provide adequate etching rates and do not damage surrounding metal silicide and silicon oxide structures. The etching rates of silicon nitride may be 10 Angstroms per minute and greater. Lower temperatures also allow decreasing concentrations of phosphoric acid in the etching solutions, which in some embodiments may be less than 90 weight percent. As a result, more selective etching of the silicon nitride structures may be achieved. This selectivity may be as high as hundred times relative to the silicide and silicon oxide structures. The surface conductivity of the silicide structures may remain substantially unchanged by this etching process.

Low temperature etching of silicon nitride structures using phosphoric acid solutions

A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer and having formed thereon over a second portion of the semiconductor substrate an oxide layer. The first portion and the second portion are electrically isolated by a shallow trench isolation feature. The method includes removing the oxide layer from over the second portion and recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution to form a recessed surface region. The APM solution is provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20. The method further includes epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region.

Growing community of inventors

San Jose, CA, United States of America

Gregory Nowling