International Business Machines Corporation

Globalfoundries Inc.

Gregory Gower Freeman

Marwan H Khater

Kathryn Turner Schonenberg

Andreas Daniel Stricker

David C Ahlgren

Dureseti Chidambarrao

Seshadri Subbanna

Francois Pagette

Huilong Zhu

Jae-Sung Rieh

Shreesh Narasimha

Brian Joseph Greene

Rajendran Krishnasamy

David R Greenberg

Basanth Jagannathan

William R Tonti

Jeffrey Bowman Johnson

Richard Paul Volant

Viorel C Ontalus

Huajie Chen

Rama Divakaruni

Paul S Chang

Kenneth Jay Stein

Timothy James McArdle

Siyuranga O Koswatta

Christopher D Sheraw

Bhupesh Chandra

Shwu-Jen Jeng

Dechao Guo

Judson Robert Holt

Geng Wang

Yanli Zhang

Chengwen Pei

Douglas Duane Coolbaugh

Arvind Kumar

Omer H Dokumaci

Anna Wanda Topol

James Douglas Warnock

Hiroyuki Akatsu

Kam Leung Lee

Matthew W Stoker

Christopher M Schnabel

Adam D Ticknor

J Campbell Scott

Daniel J Poindexter

Sangameshwar Saudari

Steven H Voldman

Qingqing Liang

John Joseph Pekarik

Gregory John Uhlmann

Anthony I Chou

Robert Allen Groves

William K Henson

Anil Kumar Chinthakindi

Werner A Rausch

Nivo Rovedo

Jay William Strane

Stephen Arthur St Onge

David Charles Sheridan

Leon Jacob Sigal

Claude Ortolland

Paul Stephen McLaughlin

Mahender Kumar

Jian Yu

Xiaomeng Chen

Fen Fen Jamin

Kevin McStay

Ning Su

Hasan Munir Nayfeh

Bachir Dirahoui

David Angell

Feng-Yi Huang

Xudong Wang

Scott Taylor

Feng Yi Huang

K T Schonenberg

Stephen A STONGE

Jae-Sung c/o Ibm United Kingdom Ltd Rieh

A sensor for on-chip monitoring the effects of operating conditions on a circuit, Integrated Circuit (IC) chips including the sensors, and a method of monitoring operating condition effects on-chip circuits, e.g., for the occurrence of electromigration. The sensor includes a multi-fingered driver associated with a monitored circuit, sensitive to known circuit parameter sensitivities. Sense and control logic circuit selectively driving the multi-fingered driver, and selectively monitoring for an expected multi-fingered driver response.

On-chip sensor for monitoring active circuits on integrated circuit (IC) chips

Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.

Methods of modulating the morphology of epitaxial semiconductor material

An inverter circuit for reducing runaway current due to applied voltage stress and temperature conditions comprises: first and second field effect transistor (FET) devices of opposite device polarities for driving a connected second stage device having a connected 2stage first and second FET devices, each 2stage device having a respective input gate terminal. The first FET and second FET devices have a respective output drive terminal, a first conductive structure connects the first FET output drive terminal to the input gate terminal of each the first and second connected FET device and further connects the first FET output drive terminal to the second FET output drive terminal through a ballasting resistor device. A second separate conductive structure connects the second FET output drive terminal to the input gate terminals and includes a path further connecting the second FET output drive terminal to the first FET output drive terminal through the ballasting resistor device.

Reducing thermal runaway in inverter devices

An efficient method of calculating maximum current limits for library gates in which a current limit includes the impact of self-heating effects associated with the maximum current. A maximum current solution is obtained in a self-consistent fashion, providing a way of determining the self-consistent solution in a rapid fashion without extensive numerical calculations or simulations. The present method provides a practical approach for characterizing a large library of gates for use in CMOS designs.

Method for an efficient modeling of the impact of device-level self-heating on electromigration limited current specifications

A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.

Semiconductor device having diffusion barrier to reduce back channel leakage

A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

Stress-generating structure for semiconductor-on-insulator devices

A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.

Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels

A gated diode structure and a method for fabricating the gated diode structure use a relaxed liner that is derived from a stressed liner that is typically used within the context of a field effect transistor formed simultaneously with the gated diode structure. The relaxed liner is formed incident to treatment, such as ion implantation treatment, of the stressed liner. The relaxed liner provides improved gated diode ideality in comparison with the stressed liner, absent any gated diode damage that may occur incident to stripping the stressed liner from the gated diode structure while using a reactive ion etch method.

Gated diode structure and method including relaxed liner

Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same

The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate.

Method of creating asymmetric field-effect-transistors

The present invention, in one embodiment, provides a semiconductor device including a semiconducting body including a schottky barrier region at a first end of the semiconducting body, a drain dopant region at the second end of the semiconducting body, and a channel positioned between the schottky barrier region and the drain dopant region. The semiconducting device may further include a gate structure overlying the channel of the semiconducting body. Further, a drain contact may be present to the drain dopant region of the semiconducting body, the drain contact being composed of a conductive material and in direct physical contact with a portion of a sidewall of the semiconducting body having a dimension that is less than a thickness of the semiconducting body in which the drain dopant region is positioned.

High performance schottky-barrier-source asymmetric MOSFETs

Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.

Methods for forming high performance gates and structures thereof

Growing community of inventors

Hopewell Junction, NY, United States of America

Gregory Gower Freeman