United States of America As Represented by the Secretary of the Air Force

Gregory C Desalvo

Tony K Quach

John L Ebel

Kenichi Nakano

James S Sewell

James K Gillespie

Christopher A Bozada

G David Via

Ross W Dettmer

Thomas J Jenkins

Anders P Walker

Paul D Cassity

An etching based semiconductor wafer thinning arrangement usable as an improved alternative to the usual grinding and polishing wafer thinning. The thinned wafer includes a structurally enhancing wafer backside grid array of original wafer thickness semiconductor material with grid cells surrounding individual thinned wafer areas and serving to improve the strength and physical rigidity characteristics of the thinned wafer. Preferably this grid array is supplemented with an additional, wafer periphery-located, backside ring of semiconductor material also of original wafer thickness. Ability to avoid a wafer front side mounting during thinning accomplishment, fast etching, reduced wafer breakage, enhanced wafer strength and improved wafer handling achieved with the disclosed thinning arrangement all contribute to achieved advantages over conventional wafer thinning. Gallium arsenide or other semiconductor materials are contemplated along with use in radio frequency or other integrated circuit devices of either the single transistor or complete integrated circuit components types.

Stiffened backside fabrication for microwave radio frequency wafers

An integrated circuit substrate via-hole fabrication arrangement providing for accurate determination of via-hole size and via-hole registration through use of a calibrated pattern formed into the integrated circuit substrate during portions of the normal circuit fabrication process. Initiation of the via-hole and fabrication of the calibrated pattern from one surface, such as the front side, of the integrated circuit wafer and completion of the via-hole from the opposite surface of the wafer are contemplated. The calibrated pattern may be one of several possible physical configurations and of selected dimensions usable with the process, materials and circuitry of the device being fabricated. Use of the invention in fabricating ground conductor-connected via conductors for gigahertz radio frequency-capable integrated circuits of the monolithic or mixed hybrid with monolithic type and having a ground plane element is contemplated.

Measured via-hole etching

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Bellbrook, OH, United States of America

Gregory C Desalvo