Stmicroelectronics (crolles 2) Sas

Nxp B.v.

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Gregory Bidal

Nicolas J Loubet

Dominique Golanski

Frédéric Boeuf

Francois Andrieu

Olivier Weber

Simon Jeannot

Emmanuel Josse

Sonarith Chhun

Jerome Mazurier

Fabrice A Payet

A MOS transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to a first depth in the channel region, and down to a second depth, greater than the first depth, in the source and drain regions. In the channel region, the semiconductor layer is formed from a portion of an upper semiconductor layer of a silicon on insulator substrate. In the source and drain regions, the semiconductor layer is formed by epitaxially grown semiconductor material.

MOS transistor and method of manufacturing the same

A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.

Method of manufacturing a device with MOS transistors

An integrated circuit includes a first zone for a first transistor and a second zone for a second transistor. The transistors are supported by a substrate of the silicon-on-insulator type that includes a semiconductor film on a buried insulating layer on a carrier substrate. In the second zone, the semiconductor film has been removed. The second transistor in the second zone includes a gate-dielectric region resting on the carrier substrate that is formed by a portion of the buried insulating layer). The first transistor in the first zone includes a gate-dielectric region formed by a dielectric layer on the semiconductor film.

Process for producing, from an SOI and in particular an FDSOI type substrate, transistors having gate oxides of different thicknesses, and corresponding integrated circuit

The present invention relates to method for fabricating a dual-orientation group-IV semiconductor substrate and comprises in addition to performing a masked amorphization on a DSB-like substrate only in first lateral regions of the surface layer, and a solid-phase epitaxial regrowth of the surface layer in only the first lateral regions so as to establish their (100)-orientation. Subsequently, a cover layer on the surface layer is fabricated, followed by fabricating isolation regions, which laterally separate (11&#x3b8;)-oriented first lateral regions and (100)-oriented second lateral regions from each other. Then the cover layer is removed in a selective manner with respect to the isolation regions so as to uncover the surface layer in the first and second lateral regions and a refilling of the first and second lateral regions between the isolation regions is performed using epitaxy.

Method for fabricating a dual-orientation group-IV semiconductor substrate

The present invention relates to a method for position-controlled fabrication of a semiconductor quantum dot, the method comprising: providing a substrate () of a substrate material; depositing a sacrificial layer () of a sacrificial material; depositing an active layer () of a semiconductive active material on the sacrificial layer, wherein the substrate, sacrificial and active materials are chosen such that the sacrificial layer is selectively removable with respect to the substrate and the active layer, depositing and patterning a mask layer on the active layer so as to define desired quantum-dot positions in lateral directions, fabricating a lateral access to the sacrificial layer in regions underneath the patterned mask layer; selectively removing, with respect to the substrate and the active layer, the sacrificial layer from underneath the active layer at least under the patterned mask layer; and etching the active layer under the patterned mask layer from underneath the active layer so as to assume a desired quantum-dot shape.

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Grenoble, France

Gregory Bidal