National Semiconductor Corporation

Other

Fujitsu Corporation

Virtual Silicon Technology, Inc.

Gregorio Spadea

Albert M Bergemont

John M Caywood

A nonvolatile memory array is arranged as a plurality of rows and columns of memory cell transistors. The sources of the memory cell transistors in each row of the array are electrically coupled together. The control gates of the memory cell transistors associated with a row in the array are coupled to a wordline associated with that row. The drains of the memory cell transistors in a column of the array are coupled to a bitline associated with that column. A source transistor is associated with each row and has its source coupled to a common source line, its drain coupled to the sources of all memory cell transistors in that row, and a gate coupled to the wordline. An array of split-gate nonvolatile memory cells is also disclosed.

Common source EEPROM and flash memory

The amount of current flowing in the bitline during reading of a memory cell which is in the conductive state, hereinafter called the memory cell current, can be amplified manifold by changing the above mentioned select transistors to a novel device which is described in detail. The increase of the area of the said memory arrays due to the replacement of said select transistor with the novel device is very small. In addition the novel device can be built within the pitch of said select transistor, which is the pitch of the bitline. The novel device can be used in many types of semiconductor memories, as described in the various embodiments. Static random access semiconductor memories can also benefit from the use of the novel devices.

Non-volatile memory arrangement having nanocrystals

A non-volatile memory array includes memory cells connected in a common source arrangement and formed in columns of isolated well regions so that Fowler-Nordheim tunneling is used for both write and erase operations of the memory cells. The memory arrays can be formed as NOR arrays or NAND arrays. In one embodiment, the memory array of the present invention is formed as a byte alterable EEPROM with parallel access. In another embodiment, an insulated gate bipolar transistor (IGBT) is coupled to the memory cells to increase the cell read current of the memory array. When the memory array incorporates IGBTs on the bitlines, the cell read current becomes independent of the wordline voltages. Thus, the memory array of the present invention can be operated at low voltages. The use of IGBTs in the memory array of the present invention enables formation of embedded non-volatile memories in low-voltage digital integrated circuits.

Low voltage EEPROM memory arrays

A method for forming an EEPROM cell together with transistors for peripheral circuits is disclosed. The method results in having a predetermined amount of material remaining proximate to the edge of the electrode, thereby forming a structure that extends a short distance beyond the sides of the electrode. An additional method for forming an trilayer EEPROM cell together with transistors for peripheral circuits is also disclosed, which results trilayer layer being restricted to covering the electrode and a small proximate region extending over the substrate surface. Two shoulders may also be etched into the sidewalls of the oxide layer which lie along the edges of said electrode.

Method for forming an EEPROM cell together with transistor for peripheral circuits

Ions are implanted into a body, such as semiconductor substrate material, through one or more covering layers formed over the body. A thin conductive film is in contact with the covering layer prior to the ion implantation. The ions are implanted into the material through the thin conductive film. The conductive film functions to conduct away any charge which tends to accumulate in the covering layer. The conductive film thereby prevents a charge accumulation which would tend to discharge through and cause damage to the covering layer. The method is particularly useful for fabricating MOS and CMOS semiconductor devices.

Ion implantation method

The method for fabrication of a self-aligned gate CMOS structure which employs no additional masking steps as compared to the standard CMOS fabrication process, this improved process providing the advantages of self-alignment between the N+ and P+ source and drain diffusions with respect to their gate regions, and metal contact openings which do not overlap the edges of the P+ or N+ source and drain regions. The self-aligning gate region is defined by a silicon nitride gate layer. Several embodiments of the novel process are described.

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Saratoga, CA, United States of America

Gregorio Spadea