At&t Bell Laboratories

American Telephone & Telegraph Co., At&t Bell Laboratories

Gregg S Higashi

John C Bean

Clifford Alan King

Barry Irwin Miller

Leonard C Feldman

Cecilia Y Mak

Bahram Jalali-Farahani

Justin Larry Peticolas

Robert Hull

It has been found that selective metallization in integrated circuits is expeditiously achieved through a copper plating procedure. In this process, palladium silicide is used as a catalytic surface and an electroless plating bath is employed to introduce copper plating only in regions where the silicide is present. Use of this procedure yields superior filling of vias and windows with excellent conductivity.

Fabrication of electronic devices by electroless plating of copper onto

The inventive method of making a poly-Si emitter transistor (PET) comprises opening an emitter window in a dielectric (typically SiO.sub.2) layer, and depositing onto the thus exposed surface and/or into the single crystal Si material that underlies the exposed surface at least one atomic species. This deposition step is following by the conventional poly-Si deposition, dopant implantation and 'drive-in'. In a currently preferred embodiment the novel deposition step comprises a low dose, low energy As implantation (5.times.10.sup.13 -2.times.10.sup.15 atoms/cm.sup.2, 0.1-5 keV). The novel method can result in significantly improved device characteristics, e.g., in a doubling of h.sub.FE, as compared to analogous prior art PETs.

Method of making a polysilicon emitter bipolar transistor

Disclosed are strained layer heteroepitaxial structures (e.g., GeSi/Si) that can have low threading dislocation density as well as a substantially planar surface. Furthermore, a large fraction (e.g., &gt;90%) of the total surface are of the structure can be available for device processing. These advantageous features are achieved through utilization of novel 'dislocation sinks' on or in the substrate whose height parameter h is less than or about equal to the thickness of the strained heteroepitaxial layer on the substrate. Exemplarily, h.gtoreq.h.sub.c, where h.sub.c is the critical thickness associated with misfit dislocation generation in the substrate/overlayer combination.

Article comprising a lattice-mismatched semiconductor heterostructure

Patterned metal growth is obtained on a substrate by illuminating the substrate in the presence of a metal containing molecule adsorbed on the substrate. After initial illumination, the photoreacted molecules catalyze further metal growth without further illumination.

Growing community of inventors

Basking Ridge, NJ, United States of America

Gregg S Higashi