United States of America As Represented by the Secretary of the Air Force

Gregg H Jessen

Andrew J Green

Kelson D Chabak

Kevin D Leedy

Michael L Schuette

Robert C Fitch, Jr

Methods of forming a self-aligned gate (SAG) and self-aligned source (SAD) device for high Esemiconductors are presented. A dielectric layer is deposited on a high Esubstrate. The dielectric layer is etched to form a drift region. A refractory material is deposited on the substrate and dielectric layer. The refractory material is etched to form a gate length. Implant ionization is applied to form high-conductivity and high-critical field strength source with SAG and SAD features. The device is annealed to activate the contact regions. Alternately, a refractory material may be deposited on a high Esubstrate. The refractory material is etched to form a channel region. Implant ionization is applied to form high-conductivity and high Esource and drain contact regions with SAG and SAD features. The refractory material is selectively removed to form the gate length and drift regions. The device is annealed to activate the contact regions.

Self-aligned gate and drift design for high-critical field strength semiconductor power transistors with ion implantation

A monolithically integrated circuit comprising a semiconducting wafer, a metal oxide thin film semiconductor device disposed adjacent a first region of the semiconducting wafer, and a dissimilar semiconductor device disposed adjacent a second region of the semiconducting wafer and fabrication methods thereof.

Metal oxide thin film semiconductor device monolithically integrated with dissimilar device on the same wafer

An integrated circuit is provided including a first substrate with a first thermal conductivity. An active layer is deposited on the first substrate. At least one native device is fabricated on the active layer. A window is formed in the active layer, which exposes a portion of the first substrate. A non-native device is fabricated on a second substrate with a second thermal conductivity lower than the first thermal conductivity. The non-native device is flip-chip mounted in the widow on the first substrate and electrically connected to the at least one native device. The non-native device is also thermally connected to the first substrate such that heat generated by the non-native device is removed through the first substrate.

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Beavercreek, OH, United States of America

Gregg H Jessen