Intel Corporation

Grant M Kloster

Michael D Goodner

Jihperng Leu

Hyun-Mog Park

Florian Gstrein

Scott Bruce Clendenning

Shriram Ramanathan

Patricio E Romero

Patrick R Morrow

Boyan Boyanov

Rami Hourani

Kevin O'Brien

Szuya S Liao

Robert P Meagley

David H Gracias

Andrew W Ott

Lee D Rockford

Lawrence D Wong

Robert L Bristol

Chris E Barns

Peter K Moon

Vijayakumar S Ramachandrarao

Kevin P O'brien

Martin M Mitan

Chih-I Wu

Justin K Brask

James M Blackwell

Steven W Johnston

Xiaorong Morrow

David W Staines

Vijay Ramachandrarao

David Staintes

Donald Bruner

Paul B Fischer

Jeanette M Roberts

Eungnak Han

Harsono S Simka

Doug B Ingerly

Michael L McSwiney

Mansour Moinpour

Ying Zhou

Paul A Zimmerman

Michael G Haverty

Sadasivan Shankar

Tayseer Mahdi

Bob E Leet

Sean J Hearne

Scott List

Vijayakumar SubramanyaRao RamachandraRao

Lawrence Foley

Kunal Shah

Don Bruner

Xiarong Morrow

Chin-Chang Chen

Patrick Marrow

Vijayakumar RamachandraRao

Methods, device structures, and wafer treatment chemistries related to backside wafer treatments to reduce distortions and overlay errors due to wafer deformation during wafer chucking are described. A backside layer is applied to the wafer prior to chucking. The chemistry of the backside layer lowers the surface free energy of the wafer during chucking to eliminate or mitigate wafer deformation during wafer processing.

Backside wafer treatments to reduce distortions and overlay errors during wafer chucking

Integrated circuitry comprising an opaque material layer, such an interconnect metallization layer is first patterned with a maskless lithography to reveal an alignment feature, and is then patterned with masked lithography that aligns to the alignment feature. In some examples, the maskless lithography employs an I-line digital light processing (DLP) lithography system. In some examples the I-line DLP lithography system performs an alignment with IR illumination through a backside of a wafer. The maskless pattern may include dimensionally large windows within a frame around circuitry regions. A first etch of the opaque material layer may expose the alignment feature within the window, and a second etch of the opaque material may form IC features, such as interconnect metallization features.

Frame reveals with maskless lithography in the manufacture of integrated circuits

Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

Selective gate spacers for semiconductor devices

Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.

Selective deposition utilizing sacrificial blocking layers for semiconductor devices

Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of fabricating a thin metal film involves introducing precursor molecules proximate to a surface on or above a substrate, each of the precursor molecules having one or more metal centers surrounded by ligands. The method also involves depositing a metal layer on the surface by dissociating the ligands from the precursor molecules using a photo-assisted process.

Precursor and process design for photo-assisted metal atomic layer deposition (ALD) and chemical vapor deposition (CVD)

A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.

Forming layers of materials over small regions by selective chemical reaction including limiting enchroachment of the layers over adjacent regions

Polymer interlayer dielectric and passivation materials for a microelectronic device are generally described. In one example, an apparatus includes one or more interconnect structures of a microelectronic device and one or more polymeric dielectric layers coupled with the one or more interconnect structures, the polymeric dielectric layers including copolymer backbones having a first monomeric unit and a second monomeric unit wherein the first monomeric unit has a different chemical structure than the second monomeric unit and wherein the copolymer backbones are cross-linked by a first cross-linker or a second cross-linker, or combinations thereof.

Polymer interlayer dielectric and passivation materials for a microelectronic device

Method and structure for minimizing the downsides associated with microelectronic device processing adjacent porous dielectric materials are disclosed. In particular, chemical protocols are disclosed wherein porous dielectric materials may be sealed by attaching coupling agents to the surfaces of pores. The coupling agents may form all or part of caps on reactive groups in the dielectric surface or may crosslink to seal pores in the dielectric.

Sealing porous dielectric materials

Method and structure for minimizing the downsides associated with microelectronic device processing adjacent porous dielectric materials are disclosed. In particular, chemical protocols are disclosed wherein porous dielectric materials may besealed by attaching coupling agents to the surfaces of pores. The coupling agents may form all or part of caps on reactive groups in the dielectric surface or may crosslink to seal pores in the dielectric.

Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a dielectric layer utilizing a plasma, wherein the plasma comprises a porogen and substantially no oxidizing agent, and then applying energy to the dielectric layer, wherein the porogen disposed within the dielectric layer decomposes to form at least one pore.

Forming a porous dielectric layer and structures formed thereby

A method and structure for sealing porous dielectrics using silane coupling reagents is herein described. A sealant chain (silane coupling reagent) is formed from at least silicon, carbon, oxygen, and hydrogen and exposed to a porous dielectric material, wherein the sealant chain reacts with a second chain, that has at least oxygen and is present in the porous dielectric defining the pores, to form a continuous layer over the surface of the porous dielectric.

Sealing porous dielectrics with silane coupling reagents

A porous dielectric layer is formed on a substrate. Aluminum is incorporated in the porous dielectric layer with a pattern process using an Aluminum gas precursor. The incorporated Aluminum improves the mechanical properties of the porous dielectric layer.

Aluminum incorporation in porous dielectric for improved mechanical properties of patterned dielectric

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Lake Oswego, OR, United States of America

Grant M Kloster