Applied Materials, Inc.

At&t Bell Laboratories

Lam Research Corporation

American Telephone & Telegraph Co., At&t Bell Laboratories

Graham W Hills

Yuh-Jia (Jim) Su

Gerald Z Yin

Douglas L Keil

Anand Gupta

Robert W Wu

Xue-Yu Qian

Robert J Steger

Jerry Yuen Wong

Thomas D Nguyen

Ian J Morey

Yoshiaki Tanase

Robert E Ryan

Paul Arleo

Robert D Huttemann

Edward P Martin, Jr

William T Cochran

Joseph Lanucha

Morgan J Thoma

Kolawole R Olasupo

Cris W Lawrence

Agustin M Garcia

Keyvan Khajehnouri

Alain S Harrus

Catherine A Fieber

Hongzong Chew

Matt M Hamrah

Jon Henri

Ruth E Bucknall

Jenn L Yeh

A method of etching an oxide layer in a plasma etching reactor is disclosed. The method includes the steps of providing a semiconductor substrate including the oxide layer into the plasma etching reactor and flowing an etching gas that includes a fluorocarbon gas, a nitrogen reactant gas, an oxygen reactant gas, an inert carrier gas, and a hydrogen-containing additive gas into the plasma etching reactor. The method further includes etching an opening at least partially through the oxide layer using a plasma that is formed from the etching gas.

Mechanism for bow reduction and critical dimension control in etching silicon dioxide using hydrogen-containing additive gases in fluorocarbon gas chemistry

The invention improves etch uniformity across a silcon wafer surface in an RF plasma etch reactor. In a first aspect of the invention, etch uniformity is enhanced by reducing the etchant species (e.g., Chlorine) ion and radical densities near the wafer edge periphery without a concomitant reduction over the wafer center, by diluting the etchant (Chlorine) with a diluent gas which practically does not etch Silicon (e.g., Hydrogen Bromide) near the wafer edge periphery. In a second aspect of the invention, etch rate uniformity is enhanced by more rapidly disassociating Chlorine molecules over the center of the wafer to increase the local etch rate, without a concomitant hastening of Chlorine dissociation near the wafer periphery, by the introduction of an inert gas over the wafer center. In a third aspect of the invention, etch rate uniformity is enhanced by forcing gas flow from the gas distribution plate downward toward the wafer center to provide a greater concentration of Chlorine ions over the wafer center, by reducing the effective diameter of the chamber between the gas distribution plate and the wafer to approximately the diameter of the wafer. In a fourth aspect of the invention, etch rate uniformity is enhanced by reducing RF power near the wafer edge periphery, by reducing the RF pedestal to a diameter substantially less than that of the wafer.

Plasma reactor with enhanced plasma uniformity by gas addition, reduced

The invention improves etch uniformity across a silicon wafer surface in an RF plasma etch reactor. In a first aspect of the invention, etch uniformity is enhanced by reducing the etchant species (e.g., Chlorine) ion and radical densities near the wafer edge periphery without a concomitant reduction over the wafer center, by diluting the etchant (Chlorine) with a diluent gas which practically does not etch Silicon (e.g., Hydrogen Bromide) near the wafer edge periphery. In a second aspect of the invention, etch rate uniformity is enhanced by more rapidly disassociating Chlorine molecules over the center of the wafer to increase the local etch rate, without a concomitant hastening of Chlorine dissociation near the wafer periphery, by the introduction of an inert gas over the wafer center. In a third aspect of the invention, etch rate uniformity is enhanced by forcing gas flow from the gas distribution plate downward toward the wafer center to provide a greater concentration of Chlorine ions over the wafer center, by reducing the effective diameter of the chamber between the gas distribution plate and the wafer to approximately the diameter of the wafer. In a fourth aspect of the invention, etch rate uniformity is enhanced by reducing RF power near the wafer edge periphery, by reducing the RF pedestal to a diameter substantially less than that of the wafer.

Plasma reactor with enhanced plasma uniformity by gas addition, and

In one aspect, the invention is embodied in a plasma reactor for processing a semiconductor wafer, the reactor having a pedestal focus ring surrounding the periphery of the wafer for reducing the process etch rate near the wafer periphery, and plural openings through the pedestal focus ring which permit passage therethrough of particulate contamination, thereby reducing accumulation of particulate contamination near the wafer periphery. In another aspect, in order to reduce corrosive wear of the chamber walls, a removable gas distribution focus ring shields the side walls of the plasma reactor from reactive gases associated with processing of the semiconductor wafer.

Focus ring for semiconductor wafer processing in a plasma reactor

A magnetic field enhanced plasma etch reactor system and method of operation is disclosed. In the system and operation, modulated sinusoidal currents are generated and applied 90.degree. out of phase to opposing pairs of series connected electromagnets to produce a modified rotating magnetic field parallel to a substrate processed in the system. The modification of the rotating magnetic field, in turn, results in an improvement in the uniformity of the etch pattern over the upper surface of the substrate.

Method and apparatus for altering magnetic coil current to produce etch

Particles are repelled from the upper face of a wafer in a plasma chamber by inducing positive or negative charges on the substrate without generating a gas plasma above the substrate. The charges are induced in the substrate by bringing a conductive sheet carrying a DC voltage close to the underside of the substrate. The particle repelling effect may be enhanced by inducing alternating positive and negative charges in the substrate. This can be done by switching the polarity of the DC voltage applied to the conductive sheet, or alternatively by moving an actuator to repetitively ground and isolate the substrate from the chamber.

Use of electrostatic forces to reduce particle contamination in

A plasma etch process is described for simultaneously removing photoresist and etch residues, such as silicon oxide residues, remaining on a substrate from a prior polysilicon and/or polycide etch. The process comprises: (a) generating radicals in a plasma generator upstream of an etch chamber, from an etch gas mixture comprising (i) oxygen, water vapor, or a mixture of same; and (ii) one or more fluorine-containing etchant gases; and (b) then contacting the substrate containing the photoresist and residues from the previous polysilicon/polycide etch with the generated radicals in the etch chamber to remove both the photoresist and the etch residues during the same etch step.

Process for simultaneous removal of photoresist and polysilicon/polycide

The addition of a gaseous source of hydrogen radicals, such as hydrogen, ammonia or methane to oxide RIE etching chemistries, in amounts of from about 5 to about 20 percent by volume of the total gas flow, will increase the oxide etch rate while suppressing the polysilicon etch rate. This effect is more pronounced at lower wafer temperatures. This new process chemistry increases the oxide etch rate to greater than 5000 .ANG./min., improves the selectivity to polysilicon to greater than 25:1 and improves the selectivity to photoresist to greater than 6:1, without having a significant detrimental effect on the profile angle, the RIE lag and the etch rate uniformity. Selectivities of 50:1 have been achieved with less than 15% RIE lag using the chemistry CHF.sub.3, Ar, CF.sub.4 and NH.sub.3, with NH.sub.3 constituting 10 percent by volume of the gas flow.

Reactive ion etch process including hydrogen radicals

An improved process is described for forming one or more vias through an insulation layer by plasma etching to an underlying metal layer without depositing etch residues, including metal sputtered from the underlying metal layer, onto the sidewalls of the vias, which comprises, in one embodiment, using in the gaseous etchant one or more 3-6 carbon fluorinated hydrocarbons having the formula C.sub.x H.sub.y F.sub.z, wherein x is 3 to 6, y is 0 to 3, and z is 2x-y when the fluorinated hydrocarbon is cyclic and z is 2x-y+2 when the fluorinated hydrocarbon is noncyclic. One or more other fluorine-containing gases may also be used as long as the 3-6 carbon fluorinated hydrocarbons comprise at least 10 volume % of the fluorine-containing gas mixture. The fluorinated hydrocarbon gas or fluorine-containing gas mixture also may be mixed with up to 90 volume % total of one or more inert gases to control the taper of the via walls. At least about 5 sccm of the total gas flow must comprise a 3-6 carbon fluorinated hydrocarbon gas, regardless of the volume % of 3-6 carbon fluorinated hydrocarbon gas in the total gas stream flow. In another embodiment, a controlled amount of one or more nitrogen-containing gases are used with one or more fluorine-containing etchant gas wherein the amount of nitrogen-containing gas ranges from about 1 volume part nitrogen-containing gas per 15 volume parts fluorine-containing gas to about 1 volume part nitrogen-containing gas per 2 volume parts fluorine-containing gas.

Process for forming a via in an integrated circuit structure by etching

In a two-step etching process for making tapered contact openings in a dieletric, a thin layer of a material is interposed to serve as an adhesive between the dielectric and a photoresist layer the thin layer of material is chosen to remain essentially intact during undercut partial etching of the dielectric. As a result of enhanced adhesion, the photoresist layer remains more accurately positioned for subsequent anisotropic etching across the remainder of the thickness of the dielectric.

Method of taper-etching with photoresist adhesion layer

An integrated circuit is made by a technique that provides a planar dielectric over gate, source, and drain regions without over-etching of the gate contact region, In the inventive process, the contact windows are etched in the conformal dielectric prior to the planarization step, so that the etch thickness is the same for the gate as for the source/drain windows. Then, a sacrificial planarizing polymer (e.g., a photoresist) is deposited to cover the conformal dielectric and fill the etched windows. Finally, a planarizing etch-back is performed, and the polymer is removed from the contact windows. A planarized dielectric is achieved without excessive etching of the gate windows.

Method of making integrated circuits having a planarized dielectric

In a method of fabricating semiconductor integrated circuits, the effects of mobile ion contamination in a dielectric layer which has been subjected to a source of mobile ion contamination, e.g., reactive ion etching, is substantially eliminated by removing substantially only the topmost portion of the dielectric layer, e.g., 10-15 nm of an 800 nm layer, promptly after performing the step which produced the source of contamination.

Method for reducing mobile ion contamination in semiconductor integrated

A self-assigned, self-planarized metallization scheme for multilevel interconnections using self-aligned windows in integrated circuits is described. Trenches are etched into a dielectric and then, using an etch stop layer on top of the dielectric to prevent unwanted etching of the dielectric, self-aligned windows which expose portions of the substrate are etched in the dielectric. Self-aligned windows can also be formed without a mask.

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Los Gatos, CA, United States of America

Graham W Hills