Taiwan Semiconductor Manufacturing Comp. Ltd.

Grace H Ho

Chen-Hua Douglas Yu

Hung-Chang Hsieh

Shing-Chyang Pan

Shwang-Ming Jeng

Yao-Ching Ku

Ming-Che Wu

Li-Heng Chou

Jung Ting Chen

A semiconductor wafer is disclosed that includes a plurality of fields, including a plurality of alignment fields. Each alignment field includes a plurality of intra-field small scribe lane primary mark (SSPM) overlay mark pairs there around. The SSPM mark pairs allow for in-situ, non-passive intra-field alignment correction. In one embodiment, there may be between two and four alignment fields, and between two and four SSPM mark pairs around each alignment field. The SSPM marks of each mark pair may be extra scribe-lane marks.

In-situ overlay alignment

A method for preventing carbon and nitrogen penetration from a deposited overlayer into a dielectric insulating layer to improve a subsequent photolithographic patterning and anisotropic etching process including providing a semiconductor wafer having a process surface including an exposed dielectric insulating layer; and, subjecting the dielectric insulating layer to a hydrogen containing plasma treatment to form a penetration resistance to one of nitrogen containing and carbon containing species.

Method for avoiding carbon and nitrogen contamination of a dielectric insulating layer

Growing community of inventors

Tainan, Taiwan

Grace H Ho