Infineon Technologies Ag

Intel Mobile Communications Gmbh

Intel Deutschland Gmbh

Siemens Aktiengesellschaft

Intel Corporation

Ezconn Corporation

Gottfried Beer

Juergen Hoegerl

Irmgard Escher-Poeppel

Jens G Pohl

Klaus Pressel

Hans-Joachim Barth

Horst Theuss

Edward Fuergut

Olaf Hohlfeld

Werner Robl

Rainer Steiner

Markus Brunnbauer

Mathias Vaupel

Dominic Maier

Peter Kanschat

Thomas Kilger

Ulrich Wachter

Thorsten Meyer

Walter Hartner

Manfred Mengel

Jochen Dangelmaier

Heinrich Koerner

Peter Ossimitz

Magdalena Hoier

Joern Plagmann

Recai Sezi

Rainer Leuschner

Georg Meyer-Berg

Maciej Wojnowski

Alfred Haimerl

Nikolaus W Schunk

Werner Simbuerger

Christoph Kienmayer

Mehran Pour Mousavi

Urs Elrod

Christiane Brunner

Klaus Mueller

Joachim Mahler

Alfons Dehe

Khalil Hosseini

Ivan Nikitin

Andreas Wolter

Bernd Waidhas

Stefan Kolb

Guenther Ruhl

Werner Weber

Rainer Markus Schaller

Christian Geissler

Frank Pueschner

Franz Jost

Oliver Nagy

Volker Strutz

Hans-Ludwig Althaus

Thilo Stolze

Walther Pachler

Harald Witschnig

Daniel Kehrer

Wolfgang Furtner

Bernd Stadler

Josef Wittl

Bernhard Knott

Thomas Ort

Thomas Killer

Thomas Spoettl

Raimund Foerg

Cyrus Ghahremani

Juergen Hoelzl

Robert Allinger

Ottmar Geitner

Robert Bergmann

J&uuml;rgen Winterer

Andreas Munding

Jean Schmitt

Sebastian Beer

Matthias Von Daak

Jurgen Winterer

Gerhard Metzger-Brückl

Joem Plagmann

Heng Wan Jenny Hong

Juergen Schilling

Eva Wagner

A power semiconductor module includes a power semiconductor die attached to the first metallized side, a passive component attached to the first metallized side, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component.

Power semiconductor module having a direct copper bonded substrate and an integrated passive component, and an integrated power module

A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.

Method for fabricating a semiconductor and semiconductor package

A ferrite antenna is disclosed. The ferrite antenna includes a ferrite core a first main face, a second main face opposite to the first main face, and side faces connecting the first and second main faces. A first plurality of conductor wires are disposed at the first main face of the ferrite core; a second plurality of conductor wires disposed at the second main face of the ferrite core. A first connection member is disposed at a first side face of the ferrite core, the first connection member including a first plurality of connection wires; and a second connection member is disposed at a second side face of the ferrite core, the second connection member including a second plurality of connection wires; wherein the first and second pluralities of conductor wires and the first and second plurality of connection wires are interconnected in such a way that they form an antenna coil, wherein the ferrite core is disposed in the interior space of the antenna coil.

Vertical ferrite antenna including pre-fabricated connection members

A package which comprises a chip carrier made of a first material, a body made of a second material differing from the first material and being arranged on the chip carrier so as to form a cavity, a semiconductor chip arranged at least partially in the cavity, and a laminate encapsulating at least one of at least part of the chip carrier, at least part of the body and at least part of the semiconductor chip.

Laminate package of chip on carrier and in cavity

The electronic device for sensing a current comprises a semiconductor chip comprising a main face, an electronic circuit integrated in the semiconductor chip, a redistribution metallization layer disposed above the main face of the semiconductor chip, a current path formed in the redistribution metallization layer, the current path forming a resistor that is connected at two resistance defining end points to the electronic circuit for sensing a current flowing through the current path, and external contact elements connected with the redistribution metallization layer for feeding a current to be sensed into the current path.

Current sensor device having a sense resistor in a re-distribution layer

A photo-acoustic gas sensor includes a light emitter unit having a light emitter configured to emit a beam of light pulses with a predetermined repetition frequency and a wavelength corresponding to an absorption band of a gas to be sensed, and a detector unit having a microphone. The light emitter unit is arranged so that the beam of light pulses traverses an area configured to accommodate the gas. The detector unit is arranged so that the microphone can receive a signal oscillating with the repetition frequency.

Photo-acoustic gas sensor module having light emitter and detector units

A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main surface of the ceramic substrate and a second copper metallization bonded to a second main surface of the ceramic substrate opposite the first main surface. The power semiconductor module further includes a power semiconductor die attached the first copper metallization, a passive component attached the first copper metallization, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. An integrated power module and a method of manufacturing the integrated power module are also provided.

A method for manufacturing an inductor core is developed, wherein the method comprises the following: Forming a first electrical conductor on a first surface of a plate-shaped magnetic core; forming a second electrical conductor on a second surface of the plate-shaped magnetic core, which is opposite the first surface; and forming the inductor core by dicing the plate-shaped magnetic core transverse to the first electrical conductor and second electrical conductor.

Method of manufacturing an inductor core for a chip assembly and chip assembly

A semiconductor chip includes a semiconductor body having an active device region, one or more metallization layers insulated from the semiconductor body and configured to carry one or more of ground, power and signals to the active device region, and a plurality of contact terminals formed in or disposed on an outermost one of the metallization layers and configured to provide external electrical access to the semiconductor chip. A minimum distance between adjacent ones of the contact terminals is defined for the semiconductor chip. One or more groups of adjacent ones of the contact terminals have an electrical or functional commonality and a pitch less than the defined minimum distance. A single shared solder joint can connect two or more of the contact terminals of the semiconductor chip to one or more of contact terminals of a substrate such as a circuit board, an interposer or another semiconductor chip.

Semiconductor chip having a dense arrangement of contact terminals

A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.

Embedded chip packages and methods for manufacturing an embedded chip package

Method for producing chip assemblies that include semiconductor chip arrangements, each semiconductor chip arrangement including a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.

Method for producing a number of chip assemblies and method for producing a semiconductor arrangement

An insulated chip comprising a semiconductor chip comprising at least one chip pad and an electrically insulating layer surrounding at least part of the semiconductor chip.

Insulated die

A semiconductor device package includes an electronic component and an electrical interconnect. The electronic component is attached to the electrical interconnect. The electrical interconnect is configured to electrically couple the electronic component to external terminals of the semiconductor device package. The electrical interconnect has a first main face facing the electronic component and a second main face opposite the first main face. The semiconductor device package further includes a first semiconductor chip facing the second main face of the electrical interconnect.

Semiconductor device having a chip under package

Growing community of inventors

Nittendorf, Germany

Gottfried Beer