Texas Instruments Corporation

Gordon P Pollack

Satwinder S Malhi

Amitabh Jain

Clarence W Teng

William F Richardson

William R Hunter

Theodore Warren Houston

Robert H Havemann

Robert R Doering

Robert H Eklund

Ravishankar Sundaresan

Srinivasan Chakravarthi

Clyde R Fuller

Mishel Matloubian

Christopher Slawinski

Suresh Potla

Dave Monahan

Donald M Bordelon

The present invention provides, in one embodiment, a process for fabricating a metal oxide semiconductor (MOS) device (). The process includes forming a gate () on a substrate () and forming a source/drain extension () in the substrate (). Forming the source/drain extension () comprises an abnormal-angled dopant implantation () and a dopant implantation (). The abnormal-angled dopant implantation () uses a first acceleration energy and tilt angle of greater than about zero degrees. The dopant implantation () uses a second acceleration energy that is higher than the first acceleration energy. The process also includes performing an ultrahigh high temperature anneal of the substrate (), wherein a portion () of the source/drain extension () is under the gate ().

Source/drain extension implant process for use with short time anneals

An embodiment of the invention is an integrated circuithaving halo atomsconcentrated at a gate side of a channel region and impurity atomswithin the channel region. Another embodiment of the invention is a method of manufacturing an integrated circuit that includes the implantation of impurity atomsinto a semiconductor substrate

Gate edge diode leakage reduction

A method for forming a mesa-isolated SOI transistor using a split-process polysilicon gate including the steps of depositing a layer of buried oxide (14) on a silicon substrate (12), depositing an SOI layer (16) on buried oxide layer (14), and forming a gate oxide layer (18) on the SOI layer (16). Further steps are to form a gate polysilicon mesa (20) on the gate oxide layer, and an SOI mesa (28) on gate polysilicon mesa (20) and forming an oxide sidewall (26) on the gate polysilicon mesa (20) and SOI mesa (28). A gate electrode (38) is the formed along with an oxide sidewall (36). Implanting gate electrode (38) with a boron implant occurs next, after which an oxide sidewall is formed on the gate electrode (38). The gate electrode (38) is implanted with phosphorus to form source and drain region. Thereafter annealing the structure takes place.

Method for forming a mesa-isolated SOI transistor having a split-process

A method and structure for forming a trench within a semiconductor layer (12) of material is provided. A first mask structure comprising a third insulating layer (20) and a fourth insulating layer (22) is formed adjacent a semiconductor layer (12). Sidewall spacers comprising a first and second portion (30) and (32) are formed along the sidewall (25) of layers (20) and (22) and extending outwardly the refrom. A second mask structure comprising a field insulating region (36) is formed adjacent first sidewall spacer portions (30) and along semiconductor layer (12). The foot portions (34) of first sidewall spacer portions (30) are removed thereby defining an exposed area (38) between the first mask structure and second mask structure. A trench (40) may then be formed between the two mask structures and filled with dielectrical material in order to isolate a semiconductor mesa (42) from semiconductor regions (44a) and 44b).

Method and structure for forming a trench within a semiconductor layer

A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel and drain and one capacitor plate are formed essentially vertically in the bulk substrate sidewalls of the trench, and the gate and other capacitor plate are formed in two regions of material inserted into the trench and isolated from the bulk by an insulating layer. Signal charge is stored on the capacitor material inserted into the trench by an electrical connection of the bulk substrate source to the capacitor material through the insulating layer. In preferred embodiments word lines on the substrate surface connect to the upper of the inserted regions which forms the gate, and bit lines on the substrate surface form the drains. The trenches and cells are formed at the crossings of bit lines and word lines; the bit lines and the word lines form perpendicular sets of parallel lines.

dRAM cell and method

A silicon-on-insulator MOS transistor is disclosed that has an implanted region of the same conductivity type as the body underneath one or both of the extended drain and source portoins of the drain and the source with and without a BTS contact or a general body contact. With only the pocket implants, the back gate threshold voltage is enhanced to reduce the possibility of back gate current flowing. With the pocket implants and a body contact, the floating body effects are minimized. Due to the BTS contact being located as far into the source as the pocket implant extends, negligible impact is made on the device channel. Ohmic connection between the source and the body is made for example by way of silicidation.

Method of fabricating a SOI transistor with pocket implant and

An improved SOI structure 40 is provided. SOI structure 40 includes a semiconductor mesa 42 formed over a buried insulating layer 46 which overlies a substrate 48. Sidewall insulator regions 50 and 52 are formed along sidewalls 54 and 56, respectively, of semiconductor mesa 42. Sidewall spacers 62 and 64 are formed along sidewall insulator regions 50 and 52, respectively. Sidewall spacers 62 and 64 each include respective foot regions 66 and 68. Foot regions 66 and 68 effectively shift undercut areas 74 and 76 laterally away from semiconductor mesa 42.

Semiconductor over insulator mesa

A method and structure for forming a trench within a semiconductor layer (12) of material is provided. A first mask structure comprising a third insulating layer (20) and a fourth insulating layer (22) is formed adjacent a semiconductor layer (12). Sidewall spacers comprising a first and second portion (30) and (32) are formed along the sidewall (25) of layers (20) and (22) and extending outwardly therefrom. A second mask structure comprising a field insulating region (36) is formed adjacent first sidewall spacer portions (30) and along semicondcutor layer (12). The foot portions (34) of first sidewall spacer portions (30) are removed thereby defining an exposed area (38) between the first mask structure and second mask structure. A trench (40) may then be formed between the two mask structures and filled with dielectrical material in order to isolate a semiconductor mesa (42) from semiconductor regions (44a) and 44b).

Method for forming a trench within a semiconductor layer of material

Semiconductor over insulator mesa and method of forming the same

A silicon-over-insulator transistor is provided having a semiconductor mesa (40) overlying a buried oxide (42). Insulating regions (50) are formed at the sides of the semiconductor mesa (40). An oxidizable layer (56) is formed over the mesa's insulating region (46). This oxidizable layer (56) is then anisotropically etched, resulting in oxidizable sidewalls (60). An optional foot (70) may be formed at the bottom edge of the oxidizable sidewalls (76). These oxidizable sidewalls (76) are then oxidized, resulting in a pure oxide sidewall (64). The gate (66) is then formed over the pure oxide sidewalls (64) and a gate oxide (62).

Thin oxide sidewall insulators for silicon-over-insulator transistors

The present invention is described in conjunction with the fabrication of a dRAM cell which an important application of the present invention. The described cell provides a one-transistor/one-capacitor dRAM cell structure and array in which the cell transistor is formed on the sidewalls of a substrate trench containing the cell capacitor; the word and bit lines cross over this trench. This stacking of the transistor on top of the capacitor yields a cell with minimal area on the substrate and solves a problem of dense packing of cells. One capacitor plate and the transistor channel and source region are formed in the bulk sidewall of the trench and the transistor gate and the other plate of the capacitor are both formed in polysilicon in the trench but separated from each other by an oxide layer inside the trench. The signal charge is stored on the polysilicon capacitor plate by an electrical connection of the source region with the polysilicon capacitor plate, which is provided by the described embodiment of the invention. Another embodiment of the present invention is an interconnection between a surface conductor and the surface of the substrate. This embodiment uses a conductive plug formed between the conductor and the substrate to form an interconnection using a minimum of surface area of the substrate.

Method for forming a buried lateral contact

Method of making dRAM cell with trench capacitor

Refractory metals, refractory metal silicide, and polysilicon/refractory metal silicide sandwich structures integrated circuits are etched using carbonyl chemistry. That is, the deposited material is plasma etched using an etchant gas mixture which contains a gas, such as CO2, which can dissociate to provide carbonyl groups (CO) or, in combination with halogen sources, carbonyl halide radicals.

Plasma etching of refractory metals and their silicides

An integrated circuit isolation technology wherein the nitride-sidewall methods of the prior art are improved by performing an undercut and backfill before the second nitride (the sidewall nitride which prevents encroachment) is added to the first nitride (which covers the moat areas). Thus, the butt joint between the two nitrides is made more secure, and localized bird's-beaking at the butt joint between the moat nitride and the sidewall nitride does not occur.

Growing community of inventors

Richardson, TX, United States of America

Gordon P Pollack