Semiconductor Components Industries, LLC

Plasma-therm, Inc.

Motorola Corporation

Other

Gordon M Grivna

Gary Horst Loechelt

Linnell Martinez

David Pays-Volard

Russell Westerman

Chris Johnson

Prasad Venkatraman

David J Johnson

Zia Hossain

John Michael Parsey, Jr

Balaji Padmanabhan

Peter J Zdebel

Michael John Seddon

Ali Salih

Jefferson W Hall

Mohammed Tanvir Quddus

Francine Y Robb

Shanghui Larry Tu

George Chang

Rich Gauldin

Peter Austin Burke

Sudhama C Shastri

Yusheng Lin

Peter Moens

Stephen St Germain

Mingjiao Liu

Jason Michael Doub

Jay A Yoder

David D Marreiro

Ralph N Wall

Dennis Lee Conner

Michael Thomason

Earl D Fuchs

William F Burghout

Kirk K Huang

Meng-Chia Lee

Thierry Lazerand

Shamsul Arefin Khan

Francis J Carney

Takashi Noma

Bruce A Bernhardt

Chun-Li Liu

Sungkwon C Hong

Gregory W Grynkewich

David T Price

Mihir Mudholkar

Clarence J Tracy

James P Morgan

Syd R Wilson

Peter Coppens

John L Freeman, Jr

Rick Carlton Jerome

Thomas Keena

Harold Anderson

Toshihiro Hachiyanagi

Scott M Donaldson

Eddy De Backer

Dwarakanath Geerpuram

Robert L Duffin

Ken Mackenzie

Carroll Casteel

Thomas S Roche

Karl J Johnson

Miki Ichiyanagi

Freddy De Pestel

Wentao Qin

Thomas Anderson

Hank Hukyoo Shin

Hou Nion Chan

Hiroyuki Suzuki

Jaume Roig-Guitart

Abhishek Banerjee

Jeffrey Pearse

Ernest Schirmann

Peter McGrath

Duane B Barber

Marino J Martinez

Alexander Young

Steven M Etter

Lawrence S Klingbeil, Jr

Herbert De Vleeschouwer

Jaume Roig Guitart

Masafumi Uehara

James Sellers

Gennadiy Nemtsev

Yingping Zheng

Wayne A Cronin

Sauvik Chowdhury

Ki Chang

Irene S Wan

Christopher Lawrence Rexer

Gordon C Ma

Kirby F Koetz

Hui Wang

Diann Dow

Stevan Gaurdello Hunter

Donald Zaremba

James M Parsey, Jr

Dorai Iyer

James Kimball

The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a clamping electrode for electrostatically clamping the work piece to the work piece support; providing a mechanical partition between the plasma source and the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.

Method and apparatus for plasma dicing a semi-conductor wafer

In one general aspect, an apparatus can include a substrate having a semiconductor region, and a trench defined in the semiconductor region and having a sidewall. The apparatus can include a shield electrode disposed in the trench and insulated from the sidewall of the trench by a shield dielectric, the shield dielectric having a low-k dielectric portion and a high-k dielectric portion. The apparatus can include a gate electrode disposed in the trench and at least partially surrounded by a gate dielectric, and an inter-electrode dielectric disposed between the shield electrode and the gate electrode.

Shielded gate trench power MOSFET with high-k shield dielectric

In a general aspect, a fan-out wafer level package (FOWLP) can include a semiconductor die having an active surface, a backside surface, a plurality of side surfaces, each side surface of the plurality of side surfaces extending between the active surface and the backside surface, a plurality of conductive bumps disposed on the active surface, and an insulating layer disposed on a first portion of the active surface between the conductive bumps. The FOWLP can also include a molding compound encapsulating the backside surface, the plurality of side surfaces, and a second portion of the active surface between the conductive bumps and a perimeter edge of the active surface. The FOWLP can also include a signal distribution structure disposed on the conductive bumps, the insulating layer and the molding compound. The signal distribution structure can be configured to provide respective electrical connections to the plurality of conductive bumps.

Fan-out wafer level packaging of semiconductor devices

An apparatus for singulating a layer of material on a semiconductor substrate includes a chamber. The chamber is configured for supporting a semiconductor substrate attached to a carrier substrate, the semiconductor substrate can include a plurality of die formed as part of the semiconductor substrate and separated from each other by singulation lines and a layer of material disposed over a major surface of the semiconductor substrate. In some examples, the singulation lines terminate so that the layer of material extends over the singulation lines. The apparatus includes a pressure transfer vessel inside the chamber and a compression structure movably associated with the chamber. The compression structure can be configured so that the pressure transfer vessel is interposed between the semiconductor substrate and the compression structure. The compression structure and the pressure transfer vessel are adapted to apply pressure to the entire semiconductor substrate to singulate the layer of material that extends over the singulation lines.

Method of separating electronic devices having a back layer and apparatus

In a general aspect, a semiconductor device assembly includes a first portion of a semiconductor substrate; a second portion of the semiconductor substrate, and a semiconductor device layer disposed on the first portion of the semiconductor substrate and the second portion of the semiconductor substrate. The semiconductor device layer includes a first semiconductor device disposed on the first portion of the semiconductor substrate, and a second semiconductor device disposed on the second portion of the semiconductor substrate. The assembly also includes an isolation trench defined in the semiconductor substrate that has a dielectric material disposed therein. The isolation trench is disposed between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate, and electrically isolates the first portion of the semiconductor substrate from the second portion of the semiconductor substrate. The semiconductor device layer excludes the isolation trench.

Monolithic semiconductor device assemblies

A method of manufacturing an electronic device includes providing a work piece comprising a first material, a first side, a second side opposite to the first side, and a first CTE. The method includes providing recesses extending into the work piece from the first side and comprising a pattern. The method includes providing a second material comprising a second CTE within the recesses and over the first material between the recesses. The method includes providing a third material comprising a third CTE over one of the second side or the second material. The third CTE and the second CTE are different than the first CTE.

Semiconductor devices with dissimlar materials and methods

A method for processing electronic die includes providing a substrate having a plurality of electronic die formed as part of the substrate and separated from each other by spaces. The method includes placing the substrate onto a first carrier substrate. The method includes plasma etching the substrate through the spaces to form singulation lines adjacent the plurality of electronic die. The method includes exposing the plurality of electronic die to solvent vapors, such as heated solvent vapors, under reduced pressure to reduce the presence of residual contaminants resulting from the plasma etching step.

Method of reducing residual contamination in singulated semiconductor die

A semiconductor device includes a region of semiconductor material having a first side and a second side opposite to the first side. Active device structures are adjacent to the first side, the active device structures comprising source regions and gate electrodes. A first gate conductor is at the first side electrically connected to the gate electrodes, a drain region is at the second side, a second gate conductor is at the second side, and through-semiconductor vias extending from the first side towards the side and electrically connecting the first gate electrode to the second gate electrode. A source electrode is at the first side electrically connected to the source regions, and a drain electrode is at the second side electrically connected to the drain region. The through-semiconductor vias are electrically isolated from the source regions and the drain region. The structure provides a gate/drain up with a source-down configuration.

Structures and methods for source-down vertical semiconductor device

A process can be used to allow processing of thin layers of a workpiece including dies. The workpiece can include a base substrate and a plurality of layers overlying the base substrate. The process can include forming a polymer support layer over the plurality of layers; thinning or removing the base substrate within a component region of the workpiece, wherein the component region includes an electronic device; and singulating the workpiece into a plurality of dies after thinning or removing the base substrate. In another aspect, an electronic device can be formed using such process. In an embodiment, the workpiece may have a size corresponding to a semiconductor wafer to allow wafer-level, as opposed to die-level, processing.

Process of forming an electronic device including a polymer support layer

A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.

Semiconductor device and method for supporting ultra-thin semiconductor die

A semiconductor device includes a work piece comprising a first material, a first side, a second side opposite to the first side, and a first coefficient of thermal expansion (first CTE). Recesses extend into the work piece from the first side and includes a pattern. A second material having a second CTE is within the recesses and is over the first material between the recesses; and A third material having a third CTE is over one of the second side or the second material. The third CTE and the second CTE are different than the first CTE.

In a general aspect, a semiconductor device assembly can include a semiconductor substrate that excludes a buried oxide layer. The semiconductor device assembly can also include a first semiconductor device stack disposed on a first portion of the semiconductor substrate, and a second semiconductor device stack disposed on a second portion of the semiconductor substrate. The semiconductor device assembly can further include an isolation trench having a dielectric material disposed therein, the isolation trench being disposed between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate. The isolation trench can electrically isolate the first portion of the semiconductor substrate from the second portion of the semiconductor substrate.

In a general aspect, method of producing an insulated-gate bipolar transistor (IGBT) device can include forming a termination structure in an inactive region. The inactive region at least partial surround an active region. The method can also include forming a trench extending along a longitudinal axis in the active region. A first mesa can define a first sidewall of the trench, and a second mesa can define a second sidewall of the trench. The first mesa and the second mesa can be parallel with the trench. The method can further include forming, in at least a portion of the first mesa, an active segment of the IGBT device, and, forming, in at least a portion of the second mesa, an inactive segment of the IGBT device.

Methods of manufacture for trench-gate insulated-gate bipolar transistors (IGBTs)

A semiconductor device includes a substrate comprising a first material, a first major surface, and a second major surface opposite to the first major surface, the first material having a first coefficient of thermal expansion (CTE). A filled recessed structure having recesses extends into the substrate and has a pattern in a plan view. The recesses are spaced apart so that part of the substrate is interposed between each of the recesses, and a second material different than the first material is in the recesses. The second material has a second CTE. A structure is proximate to the first major surface over the filled recessed structure and has a third CTE. The third CTE and the second CTE are different than the first CTE. The filled recessed structure reduces stresses between the substrate and structure. In some examples, the structure comprises a MIM capacitor. In other examples, the structure comprises a heterojunction semiconductor material.

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Mesa, AZ, United States of America

Gordon M Grivna