Advanced Micro Devices Corporation

Gopi Ganapathy

Robert C Thaden

Thang M Tran

David B Witt

Stephen C Horne

Brian D McMinn

Michael D Goddard

Stephen Charles Kromer

Steve Horne

A hardware simulation system is disclosed which includes a high frequency clock which is gated with a system clock to produce a high frequency enabled clock. The high frequency enabled clock is used to clock an edge triggered latch within the hardware simulation system. Thus, the system advantageously emulates level sensitive latches using edge triggered latches.

Simulation by emulating level sensitive latches with edge trigger latches

A method for converting a multiple-phase circuit to single-clock-edge circuit includes the steps of receiving a data signal at an input terminal, receiving a system clock signal having a system clock frequency and receiving a phase clock signal having a frequency divided from the system clock frequency. The data signal is transferred to an output terminal when the phase clock signal is active and latched upon the occurrence of an edge transition of the system clock signal when the phase clock signal is active. When the phase clock signal is inactive, the latched data signal is latched again upon the occurrence of the edge transition of the system clock signal. The latched data signal is transferred to the output terminal when the phase clock signal is inactive.

Simulating multi-phase clock designs using a single clock edge based

A microprocessor circuit is provided that allows the internal microprocessor clock speed to vary depending upon a register that can be programmed by software. In addition, the drive strength of the internal clock generator may similarly be varied by software programming. The programmer or user of the microprocessor may change the internal clock speed such that the microprocessor operates at a first frequency or at a second frequency depending upon the performance requirements. A lower frequency of operation may be selected for low power consumption and low EMI, while a higher frequency of operation may be selected for computational intensive and high performance applications.

Microprocessor with software switchable clock speed and drive strength

An latch circuit includes an input line receiving electrical signals from a bus, a latch for conducting electrical signals from the precharged bus to a receiving circuit, and a structure for enabling the latch only when data is driven onto the bus.

Circuit for delaying data latching from a precharged bus and method

A test circuit and test technique for scan testing integrated circuits includes scan cells or capture scan elements arranged in a pseudo master slave configuration. The testing technique utilizes a first independent scan cell as a master stage and a second independent scan cell as a slave stage for propagating data through the IC. The test circuit and test techniques are highly advantageous because of minimal structural overhead. However, the scan cells must be loaded twice to recover the test data because half of the test data is lost when the data is propagated through the IC. The shift register inputs of one scan cell are generally coupled to shift register outputs of other scan cells. Each scan cell generally only includes one latch element.

Pseudo master slave capture mechanism for scan elements

A distributed clock generation scheme is provided for a microprocessor that reduces electromagnetic interference and power consumption. Rather than using a single, large internal clock generator circuit that meets the drive requirements of the remaining circuitry upon the microprocessor die, a plurality of smaller clock generator circuits are distributed across the die, each generating clock signals to drive a separate portion of the microprocessor circuitry. Each of the distributed clock generator circuits may be load matched with respect to the others to minimize the skew between clock signals, and each receives a synchronized timing signal provided from a master timing distribution circuit. As a result of the distributed clock generation scheme, the amount of current and the rate at which current is sourced or sunk at a given location on the semiconductor die is reduced, thereby reducing electromagnetic interference and increasing the signal to noise ratio. In addition, the loading upon the distributed clock generators due to the internal routing of the clock signals is decreased, also reducing electromagnetic interference and power consumption.

Microprocessor with distributed clock generators

A test circuit and test technique for scan testing integrated circuits is disclosed. The test circuit includes a drive 1 or drive 0 scan element which utilizes fewer transistors than conventional scan latches. The testing technique utilizes the clock input to the latches in the ICs for propagating data through the latches. The test circuit and test techniques may be used with microprocessors and particularly RISC microprocessors. The test technique includes coupling a drive 1 or drive 0 element to a logic element coupled to a general latch. The drive 1 or drive 0 scan element allows the general latch to be clocked by a clock signal such as a .phi.1 clock signal or .phi.2 clock signal.

Full scan optimization technique using drive one/drive zero elements and

An apparatus for synchronizing a plurality of asynchronous circuits during testing operations is provided. The apparatus includes first and second clock inputs, a test mode input, and an output. The apparatus receives a first clock signal from a first clock at the first clock input, and a second clock signal from a second clock at the second clock input. Responsive to the state of a test mode signal at the test mode input, the apparatus generates either the first clock signal or the second clock signal at the output. A first circuit is arranged to be driven by the output of the apparatus, while a second circuit is driven by one of the first or second clocks. Consequently, the first and second circuits are driven by different clocks when the test mode signal is in one state, and driven by the same clock when the test mode signal is in another state. Because the first and second circuits are driven by the same clock during testing operations, the timing of the communications between the circuits is predictable, making it possible to perform certain testing techniques that are not possible when the timing of inter-circuit communication is not predictable.

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Austin, TX, United States of America

Gopi Ganapathy