Samsung Electronics Co., Ltd.

Gongheum Han

Youngsik Kim

Seunghyun Cho

Sangyun Kim

Sunggeun Do

Chang-Yong Lee

A memory device includes a word line driver circuit, which can advantageously reduce gate stress on a transistor using a lower high voltage that varies with a command, and an operating method of the memory device. The memory device includes a plurality of memory blocks, provides a high voltage or the lower high voltage to a variable high voltage line in response to a block select signal, and changes a level of the lower high voltage to a low voltage level, a medium voltage level, or a high voltage level based on the command. The memory device applies the lower high voltage to gates of P-type metal oxide semiconductor (PMOS) transistors connected to a word line driving signal, which drives word lines of non-selected memory blocks among the plurality of memory blocks.

Word line driver circuits for memory devices and methods of operating same

A semiconductor memory device includes a plurality of banks; a peripheral circuit configured to send data to and receive data from the plurality of banks; and data lines configured to connect the plurality of banks and the peripheral circuit, wherein the plurality of banks are disposed such that a sum of lengths of data transfer paths of the data lines connecting the peripheral circuit and at least two banks, among the plurality of banks, activated at a same time is uniformly maintained.

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Hwaseong-si, South Korea

Gongheum Han