International Business Machines Corporation

Gobinda Das

Franco Motika

Steven J Duda

Paul M Gaschke

Erich Berndlmaier

Thomas L Viau

Frank Daniel Egitto

David Brian Stone

William Joseph Murphy

Natalie Barbara Feilchenfeld

Klaus D Beyer

Elizabeth F Foster

Matthew J Farinelli

Stephen Joseph Fuerniss

Ernest Bassous

Michael R Poponiak

James Steven Kamperman

Michael R Scheuermann

Samuel McKnight

Frederic Beaulieu

Donald J Mikalsen

Adreanne Kelly

John F Vetrero

Tsu-Hsing Yeh

Charles J Blasi

Frederick L Taber, Jr

Angelo M Giaimo

Techniques for bond pad fabrication are provided. In one aspect, a method of forming a bond pad comprises the following steps. At least one alloying element is selectively introduced to at least a portion of at least one surface of the bond pad. The at least one alloying element is diffused into at least a portion of the bond pad through one or more thermal cycles. The at least one alloying element may be selectively introduced to the bond pad by depositing an alloying element layer comprising the at least one alloying element onto the bond pad and patterning and etching at least a portion of the layer.

Techniques for improving bond pad performance

A method for testing external connections to semiconductor devices. The method includes providing an external electrical path between selected external connections on the semiconductor devices.

TFI probe I/O wrap test method

A structure for testing external connections to semiconductor devices. The structure includes an external electrical path between selected external connections on the semiconductor devices.

A nonresilient rigid test probe arrangement which is designed for testing the integrity of silicon semiconductor device wafers or chips, and which eliminates pliant conditions encountered by current text fixtures, which are adverse to the attainment of satisfactory test results with rigid probes. The test system interface assembly includes a rigid ceramic substrate which forms a pedestal over which the rigid probe makes electrical contact. A PC board is located on the opposite side of the ceramic substrate. A clamp ring retains the PC board to a test head system with mating precision reference surfaces formed therebetween. Pogo pin connectors extend between the PC board and the test head system. A stiffening element having a control aperture is bolted through the PC board to the clamp ring, all of which form a rigid test probe arrangement.

Wafer probe interface arrangement with nonresilient probe elements and support structure

A probe system for electrical contact testing of a row of densely spaced wire bonding pads is provided comprising a plurality of probes, with each probe having a tip offset from the probe center axis. The probes may be mounted in a housing having an upper die and a lower die, and the lower die may be offset from the upper die. The probes are pivotally mounted in the holes of the upper die, and the probe bodies are convexly curved and extend down into the holes of the lower die. The bevel tipped probes may be arranged in two staggered and parallel rows of probes, with the tip of each probe oriented along the centerline formed between the two row of probes. The probes may be closely spaced in each row. The tips of the probes in one row are oriented 180 degrees with respect to the probes in the opposite row. The tips of each probe may also comprise a tip located along the center axis or a double bevel surface forming a tip at the apex of the two bevel surfaces.

Off-axis contact tip and dense packing design for a fine pitch probe

Disclosed is a sculpted probe pad and a gray scale etching process for making arrays of such probe pads on a thin flexible interposer for testing the electrical integrity of microelectronic devices at terminal metallurgy. Also used in the etching process is a novel fixture for holding the substrate and a novel mask for 1-step photolithographic exposure. The result of the invention is an array of test probes of preselected uniform topography, which make ohmic contact at all points to be tested simultaneously and nondestructively.

Gray scale etching for thin flexible interposer

A multi-layer ceramic module comprises a multi-layer ceramic substrate having an upper side and a lower side, at least one semiconductor chip mounted on the upper side of the substrate, a plurality of module pins projecting from the lower side of the substrate and at least one decoupling capacitor mounted on the lower side of the substrate between adjacent ones of the module pins.

Multi-layer ceramic substrate decoupling

A method for making a structure for bonding to a conductive pad on a semiconductor substrate is described. The structure comprises a glassy passivating layer with a thickness of at least 3 microns deposited over the conductive pad. The passivating layer defines an aperture which exposes a portion of the conductive pad. A metal bump covers the portion of the conductive pad exposed in the aperture and further extends over the edges of the glassy passivating layers so as to form a seal between the conductive pad and the glassy passivating layer. A subsequent thermal compression bonding operation on such structure does not cause fractures in the glassy passivating layer due to its thickness.

Metal bump for a thermal compression bond and method for making same

A structure for bonding to a conductive pad on a semiconductor substrate is described. The structure comprises a glassy passivating layer with a thickness of at least 3 microns deposited over the conductive pad. The passivating layer defined an aperture which exposes a portion of the conductive pad. A metal bump covers the portion of the conductive pad exposed in the aperture and further extends over the edges of the glassy passivating layer so as to form a seal between the conductive pad and the glassy passivating layer. A subsequent thermal compression bonding operation on such structure does not cause fractures in the glassy passivating layer due to its thickness.

A method for fabricating bipolar semiconductor devices of large scale integration in which the formation of pipes, which result in shorts or leakages between two conductivity types of the semiconductor devices, is minimized. Prior to forming the emitters in the bipolar transistors, nucleation sites for crystallographic defects such as dislocation loops are formed in the base region near its surface. The emitters are then formed in base regions containing the nucleation sites and the sites are converted into electrically harmless dislocation loops during diffusion of the emitter impurity. Preferably, the nucleation sites are formed by implanting non-doping impurities, such as helium, neon, argon, krypton, xenon, silicon, and oxygen.

Growing community of inventors

Hopewell Junction, NY, United States of America

Gobinda Das