Xilinx, Inc.

Xilnix, Inc.

Glenn O'Rourke

Raghunandan Chaware

Inderjit Singh

Ganesh Hariharan

Xiao-Yu Li

Qi Xiang

Amitava Majumdar

Eric Thorne

Stephen M Trimberger

Matthew H Klein

Xiao-yu Li

Cinti Xiaohua Chen

Jongheon Jeong

Yuezhen Fan

Jae Cho

Michael M Matera

Felino E Pagaduan

Thao H T Vo

Shiying Xiong

David E Schweigler

Cinti X Chen

An integrated circuit (IC) chip package assembly apparatus and techniques for assembling IC chip packages are described. For example, a techniques for fabricating an IC package include (A) determining a first package assembly yield (PAY) across a first die pool comprising a first plurality of dies having a performance criteria within a first predefined range; (B) determining a second PAY across a second die pool comprising a second plurality of dies having a performance criteria within a second predefined range of performance criteria that is different than the first predefined range of performance criteria, the second plurality of dies comprising a portion of the first plurality of dies; and (C) generating a final assembly sequence in response to analyzing the first and second PAYs, the final assembly sequence comprising rules for combining dies in accordance with obtaining a higher of the first PAY and the second PAY.

High yield package assembly technique

Methods and apparatus are described for creating a multi-die package from a wafer without dicing the wafer into individual dies and reassembling the dies on an interposer. One example method generally includes testing a plurality of IC dies disposed on a wafer; disposing one or more connectivity layers above the plurality of IC dies, the one or more connectivity layers comprising one or more electrical conductors configured to connect together two or more of the plurality of dies in each of one or more groups of the IC dies; dicing the wafer having the one or more connectivity layers disposed above the plurality of dies into sets, each set comprising one or more of the plurality of dies, wherein the dicing is based on the one or more groups having IC dies that passed the testing; and packaging at least a portion of the sets of dies.

Multi-die wafer-level test and assembly without comprehensive individual die singulation

An example method of manufacturing a semiconductor assembly includes: forming first integrated circuit (IC) dies and dummy dies; forming an interposer wafer including a top side having first mounting sites for the first IC dies and second mounting sites for second IC dies; attaching the first IC dies to the interposer wafer at the first mounting sites and the dummy dies to the interposer wafer at the second mounting sites; processing a backside and the top side of the interposer wafer; removing the dummy dies from the top side of the interposer wafer to expose the second mounting sites; and attaching the second IC dies to the interposer wafer at the exposed second mounting sites.

Heterogeneous integration of integrated circuit device and companion device

Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal transmission path between the IC dice.

Interposer-less stack die interconnect

A method for providing charge protection to a die during formation of an integrated circuit, includes bonding the die to an interposer to form an unprotected stacked silicon component; encapsulating the unprotected stacked silicon component with a mold compound to cover at least a top surface of the die; grinding the mold compound to reduce a thickness of the mold compound; bonding a carrier wafer to the mold compound; removing the carrier wafer from the mold compound; and removing the mold compound from the top surface of the die after the carrier wafer is removed from the mold compound, to expose the top surface of the die.

Method for providing charge protection to one or more dies during formation of a stacked silicon device

A method of enabling the use of a programmable device having impaired circuitry includes determining one or more locations of the impaired circuitry of the programmable device; generating a defect map for the programmable device based on the determined locations of the impaired circuitry; generating a plurality of configuration bitstreams to implement a circuit in the programmable device; selecting one of the plurality of configuration bitstreams that does not use the impaired circuitry indicated by the defect map; and programming the programmable device with the selected configuration bitstream.

Increased usable programmable device dice

A testable circuit arrangement includes an integrated circuit (IC) package. The IC package includes a package substrate, an interposer mounted directly on the package substrate with level 1 interconnects, and at least one IC die mounted directly on the interposer with level 0 interconnects. The package substrate of the IC package is mounted directly on a connector board with a soldered ball grid array of level 2 interconnects. The level 0, level 1, and level 2 interconnects include respective power, configuration, and test interconnects. Power, configuration, and test terminals of the connector board are coupled to the power, configuration, and test interconnects of the level 2 interconnects.

Integrated circuit package testing

An apparatus relating generally to an interposer is disclosed. In such an apparatus, the interposer has a plurality of conductors and a plurality of charge attracting structures. The plurality of charge attracting structures are to protect at least one integrated circuit die to be coupled to the interposer to provide a stacked die. The plurality of conductors include a plurality of through-substrate vias.

Charge damage protection on an interposer for a stacked die assembly

A method for removing bumps from incomplete interposer die(s) and/or defective interposer die(s) of an interposer wafer is described. The method includes forming bumps on an interposer wafer; identifying at least one incomplete interposer die and/or at least one defective interposer die of the interposer wafer; and removing bumps from the at least one incomplete interposer die and/or the at least one defective interposer die of the interposer wafer.

Method for removing bumps from incomplete and defective interposer dies for stacked silicon interconnect technology (SSIT) devices

Method and apparatus for self-regulated burn-in of an integrated circuit (IC) is described. One embodiment of a method of burn-in for the IC includes: configuring programmable resources of the IC device based on a burn-in pattern to implement a load controller, the load controller having a plurality of heat core circuits. The load controller is initialized with a number of enabled heat core circuits of the plurality of heat core circuits. A junction temperature is measured in the IC device after a measurement period has elapsed. The junction temperature is compared with a set-point temperature. The number of the enabled heat core circuits is increased if the junction temperature is less than the set-point temperature, or the number of the enabled heat core circuits is decreased if the junction temperature is greater than the set-point temperature.

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Gilroy, CA, United States of America

Glenn O'Rourke