International Business Machines Corporation

Freescale Semiconductor,inc.

Other

Glenn Graham Daves

David L Edwards

Michael Jay Shapiro

Frank Louis Pompeo

Louis Bennie Capps, Jr

Ronald Edward Newhart

Hilton T Toy

Mukta G Farooq

Anand Haridass

Krishna Gandhi Sachdev

Scott M Hayes

Sushumna Iruvanti

Zhiwei Gong

Jean Audet

Herbert I Stoller

Daniel George Berger

Kelly May Chioujones

Navjot Chhabra

Michael A Paolini

Robert H Bell, Jr

Leo M Higgins, Iii

Shaji Farooq

Norman J Dauerer

Thomas Edward Cook

Jason Lee Frankel

William Frederick Shutler

John F Vetrero

Anthony Wayne Sigler

Cathy Ann Zadany

Evan G Colgan

Michael A Gaynes

David Clifford Long

Da-Yuan Shih

Sung Kwon Kang

Bruce Kenneth Furman

Sudipta Kumar Ray

Steven Paul Ostrander

Peter Jeffrey Brofman

Burton Jesse Carpenter

Kenneth Charles Marston

Douglas G Mitchell

Donald W Henderson

Jason R Wright

Jason Scott Miller

Ronald L Hering

Joseph Michael Sullivan

Peter M Elenius

Joanne Ferris

Dennis Felix Clocher

Joseph John Lisowski

Jaimal M Williamson

A method of packaging a semiconductor device is described. The method includes: attaching a first surface of a semiconductor die to a carrier; forming one or more first stud bumps on the carrier; using bond wires, electrically connecting one or more locations on a second surface of the semiconductor die to one or more first stud bumps; molding the semiconductor die, the first stud bumps, and the bond wires in an encapsulation material; removing the carrier from the bottom side of the semiconductor package exposing a portion of the first stud bumps; and attaching one or more solder balls to the exposed portion of the first stud bumps.

Method and apparatus for assembling a semiconductor package

A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are placed in a holder that is subsequently embedded in an encapsulated semiconductor device package. The ends of the signal conduits are exposed and the signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package. Holders can be provided in a variety of geometries and materials, depending upon the nature of the application. Further, multiple holders with signal conduits can be provided in a single package to provide for more complex interconnect configuration demands in, for example, system-in-a-package applications.

Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits

A method for forming a molded die assembly includes attaching a first major surface of a semiconductor die onto a package substrate; attaching a heat spreader to a second major surface of the semiconductor die, wherein the second major surface is opposite the first major surface, and wherein the semiconductor die, package substrate, and heat spreader form a die assembly; conforming a die release film to a transfer mold; closing the transfer mold around the die assembly such that the die release film is compressed against the heat spreader and a cavity is formed around the die assembly; transferring a thermoset material into the cavity; and releasing the die assembly from the die release film and the transfer mold.

Method for forming die assembly with heat spreader

A semiconductor device package having pre-formed and placed through vias and a process for making such a package is provided. One or more signal conduits are coupled to a lead frame that is subsequently embedded in an encapsulated semiconductor device package. The free end of signal conduits is exposed while the other end remains coupled to a lead frame. The signal conduits are then used as through package vias, providing signal-bearing pathways between interconnects or contacts on the bottom and top of the package and the leads.

Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits

A processor has multiple cores with each core having an associated function to support processor operations. The functions performed by the cores are selectively altered to improve processor operations by balancing the resources applied for each function. For example, each core comprises a field programmable array that is selectively and dynamically programmed to perform a function, such as a floating point function or a fixed point function, based on the number of operations that use each function. As another example, a processor is built with a greater number of cores than can be simultaneously powered, each core associated with a function, so that cores having functions with lower utilization are selectively powered down.

Multicore processor and method of use that adapts core functions based on workload execution

A method for forming through vias in a semiconductor device package prior to package encapsulation is provided. One or more signal conduits are formed through photolithography and metal deposition on a printed circuit substrate having interconnect pads. After removing photoresistive material, the semiconductor device package is built by encapsulating the signal conduits along with any semiconductor die, wire bonding, and other parts of the package. Free ends of each signal conduit are exposed and the signal conduits are used as through vias to provide signal-bearing pathways between connections from a top-mounted package to a printed circuit substrate interconnect and electrical contacts of the semiconductor die or package contacts. Using this method, signal conduits can be provided in a variety of geometric placings on the printed circuit substrate for inclusion in a semiconductor device package. A semiconductor device package incorporating the pre-fabricated through vias is also provided.

Semiconductor device packaging having substrate with pre-encapsulation through via formation

A method for assembling, and the resultant electronic module, includes attaching a chip to a substrate using a first solder interconnection array, and attaching a board to the substrate using a second solder interconnection array, which may be a single-melt or a dual-melt solder array. The second solder interconnection array resides entirely within a space defined between the board and substrate. A creep resistant structure is provided within this space for maintaining the defined space and optimizing integrity of the second solder interconnection array. The creep resistant structure may include an underfill material, balls, brackets, frames, collars or combinations thereof. Wherein the creep resistant structure is an underfill material, it is crucial that the substrate be attached to the board before either entirely encapsulating the second interconnection array with underfill material, or partially encapsulating the second solder interconnection array at discrete locations with underfill material.

Solder interconnection array with optimal mechanical integrity

A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.

Power grid structure to optimize performance of a multiple core processor

A reworkable conductive adhesive composition, comprising an epoxy based conductive adhesive containing conductive metal filler particles dispersed in a solvent-free hybrid epoxy polymer matrix.

Conductive adhesive composition

A method of removing cured conductive polymer adhesives, disclosed here as thermal interface materials, from electronic components for reclamation or recovery of usable parts of module assemblies, particularly high cost semiconductor devices, heat sinks and other module components.

Conductive adhesive rework method

A reworkable conductive adhesive composition, and method of making such, comprising an epoxy based conductive adhesive containing conductive metal filler particles dispersed in a solvent-free hybrid epoxy polymer matrix. In an additional embodiment an improved method of removing cured conductive polymer adhesives, disclosed here as thermal interface materials, from electronic components for reclamation or recovery of usable parts of module assemblies, particularly high cost semiconductor devices, heat sinks and other module components.

Thermal interface adhesive and rework

An apparatus and method for providing a multi-core integrated circuit chip that reduces the cost of the package and board while optimizing performance of the cores for use with a single voltage plane. The apparatus and method of the illustrative embodiments make use of a dynamic burn-in technique that optimizes all of the cores on the chip to run at peak performance at a single voltage. Each core is burned-in with a customized burn-in voltage that provides uniform power and performance across the whole chip. This results in a higher burn-in yield and lower overall power in the integrated circuit chip. The optimization of the cores to run at peak performance at a single voltage is achieved through use of the negative bias temperature instability affects on the cores imparted by the burn-in voltages applied.

Apparatus and method for customized burn-in of cores on a multicore microprocessor integrated circuit chip

Growing community of inventors

Fishkill, NY, United States of America

Glenn Graham Daves