Advanced Micro Devices Corporation

Semicaps Pte Ltd

Advanced Mircor Devices, Inc.

Glen P Gilfeather

Michael R Bruce

Rama Rao Goruganthu

Rosalinda M Ring

Brennan V Davis

Victoria Jean Bruce

David Harry Eppes

Daniel L Stone

Srikar V Chunduri

Jeffrey David Birdsley

Jiann Min Chin

Shawn M McBride

Donald L Wollesen

Richard C Blish

Joe W Peterson

Xia Li

Choon Meng Chua

Lian Ser Koh

Susan Xia Li

Soon Huat Tan

Richard Jacob Wilcox

Gregory A Dabney

Greg Dabney

David Bethke

Palaniappan Muthupalaniappan

Jacob Phang

Roger S Hurst

Hoo-Yin Ng

Defect analysis of a semiconductor die is enhanced in a manner that makes possible the viewing of spatial manifestations of the defect from virtually any angle. According to an example embodiment of the present invention, substrate is removed from a semiconductor die while simultaneously obtaining images of the portions of the die from which substrate is being removed. The images are taken at various points in the substrate removal process, recorded and combined together to form a three-dimensional image of selected portions of the die. The image is then used to view the selected portions, and the nature of one or more defects therein are analyzed.

Three-dimensional tomography

Apparatus for and methods of inspection using laser beam induced alteration are provided. In one aspect, an apparatus is provided that includes a laser scanning microscope for directing a laser beam at a circuit structure and a source for biasing and thereby establishing a power condition in the circuit structure. A detection circuit is provided for detecting a change in the power condition in response to illumination of the circuit structure by the laser beam and generating a first output signal based on the detected change. A signal processor is provided for processing the first output signal and generating a second output signal based thereon. A control system is operable to scan the laser beam according to a pattern that has a plurality of pixel locations, whereby the laser beam may be moved to a given pixel location and allowed to dwell there for a selected time before being moved to another pixel location.

Laser beam induced phenomena detection

The operability of light-based semiconductor die analysis is enhanced using a method and arrangement that directs light between a light source and a die. In one example embodiment of the present invention, a light source is directed to a die in a semiconductor analysis arrangement using a fiber optic cable. The analysis arrangement is adapted to use light received via the fiber optic cable to analyze the die. The analysis includes one or more light-based applications, such as stimulating a selected portion of the die with the light and detecting a response therefrom. In this manner, light can be directed to a die in a variety of analysis implementations, such as for analyzing a die in a test chamber.

Fiber optic semiconductor analysis arrangement and method therefor

Various apparatus and methods for enhancing hot-electron luminescence in an integrated circuit are provided. In one aspect, an apparatus is provided that includes a first circuit device coupled to a first voltage source that is operable to bias the first circuit device to a first voltage, and a second circuit device that has a first input coupled to the first voltage source and a junction defining a first side and a second side. One of the first and second sides is coupled to a second voltage source that is independent of the first voltage source and capable of selectively biasing the one of the first and second sides at a second voltage higher than the first voltage. The second device is operable to emit a hot-electron induced photon upon entry into saturation.

Photon beacon

An integrated circuit die having silicon on insulator (SOI) structure is analyzed in a manner that enhances the ability to detect photoemissions from the die. According to an example embodiment of the present invention, one of two or more lenses having a higher relative photon count is identified and used to analyze a semiconductor die. The die has at least a portion of the insulator of the SOI structure exposed, and photon emissions are detected using each lens via the exposed insulator in response to the die being stimulated. The number of photons detected using each lens is compared, and the lens having a higher photon count rate is identified, optimizing the photon count for the particular type of die preparation used to expose the insulator. The identified lens is then used with the high-speed detector to detect photoemissions from the die, and the detected photoemissions are used to analyze the die.

Optical analysis for SOI integrated circuits

The operability of light-based semiconductor die analysis is enhanced using a method and arrangement that can detect light leakage between a light source and a die. In one example embodiment of the present invention, a light source is directed to a semiconductor analysis arrangement using, for example, a fiber optic cable. The analysis arrangement is adapted to use light from the light source for analyzing the die. A light detection arrangement detects a condition of light leakage from the system and generates a signal representing the condition of light leakage. The generated signal can then be used to control the semiconductor analysis arrangement, such as by deactivating the light source in response to a detected leak, or by allowing the light source to function in response to not detecting a leak.

Semiconductor analysis arrangement and method therefor

Integrated circuit analysis is enhanced via a method and system for detecting defects associated with particular logic states of an integrated circuit. According to an example embodiment of the present invention, a constant current supply is applied to an integrated circuit. The voltage across the constant current supply is detected for each of a plurality of clock cycles of the integrated circuit, each clock cycle being representative of a logic state of the integrated circuit. The voltage detected at each clock cycle is compared, and the comparison is used to analyze the integrated circuit for a defect.

Constant-current VDDQ testing of integrated circuits

Semiconductor die analysis is enhanced using a system that is adapted to perturb a die in a test chamber and to detect a response from the die to the perturbation. According to an example embodiment of the present invention, a semiconductor die analysis system includes a test chamber and a docking arrangement adapted to dock with the test chamber. A die is held in the docking arrangement and is presented inside of the test chamber when the docking arrangement is docked with the chamber. Two or more perturbation devices are used to perturb the die, and controller is adapted to control the perturbation. A data acquisition arrangement receives data from the die in response to the perturbation, and the data is used for analyzing the die.

The present invention is directed to the repair of resistive circuitry in an integrated circuit die having a multitude of circuit paths. According to an example embodiment of the present invention, a semiconductor die having a resistive electrical connection is analyzed. The location of a circuit portion in the die having a resistive electrical connection is identified. Using the identified location, the resistive circuit portion is annealed and the resistivity of that circuit portion is reduced. The reduced resistivity improves the ability of the die to operate at high speeds, and makes possible the repair and subsequent use of the die in various applications.

Repair of resistive electrical connections in an integrated circuit

A semiconductor apparatus includes a semiconductor body in the form of a silicon substrate havng a plurality of active devices. A metal stack including a plurality of metal layers is operatively associated with the active devices. A plurality of conductive elements are connected to the metal stack and to a substrate in the form of for example a printed circuit board. Vias connect conductive elements with respective portions of at least some of the metal layers, with the conductive elements connected to heat absorbing members within the substrate, which is in turn connected to a heat sink external to the substrate, the vias being spaced at regular intervals so as to promote heat dissipation from the metal stack therethrough to the heat absoring members and the heat sink.

Apparatus for metal stack thermal management in semiconductor devices

Integrated circuit devices are analyzed using an integrated system adapted to obtain time-resolved information from the back side of a silicon based semiconductor chip using hot carrier emissions. According to an example embodiment of the present invention, a system is adapted to analyze a semiconductor device under test (DUT) using a plurality of sensors mounted to a microscope having an objective lens. The plurality of sensors include a global acquisition sensor, a single-point acquisition sensor, and a navigation sensor. The integrated system is adapted to use the plurality of sensors individually and simultaneously. The integrated system improves the analysis of the DUT for reasons including that it makes possible the performance of more than one type of analysis simultaneously using a single test arrangement.

Time-resolved emission microscopy system

The ability to monitor virtually any portion of semiconductor device is enhanced via a grid formed for analyzing circuitry in the semiconductor device. According to an example embodiment of the present invention, a grid having a plurality of narrow probe points is formed extending over target circuitry in a semiconductor device. The grid is accessed and used for monitoring various target circuitry within the device by accessing the part of the grid that corresponds to the portion of the target circuitry to which access is desired.

Probe grid for integrated circuit analysis

According to one aspect of the disclosure and a particular example application directed to a flip-chip packaged die, a method for acquiring a signal from a target node in the circuit side includes removing substrate via the back side of the die to form an access area over the target node. A material is deposited in the access area over the target node in such a way to form simultaneously a conductive core and an immediately adjacent insulator. The conductive core is then used to couple a test signal between the target node and the conductive core. Other aspects of the disclosure include using a focused ion-beam system to provide varying concentrations of Gallium in forming simultaneously the conductive core and the immediately adjacent insulator. These aspects significantly lessen integrated circuit analysis and testing procedures.

Method and arrangement for characterization of focused-ion-beam insulator deposition

The ability to excite virtually any portion of semiconductor device is enhanced via a grid formed for exciting circuitry in the semiconductor device. According to an example embodiment of the present invention, a grid having a plurality of narrow probe points is formed extending over target circuitry in a semiconductor device. The grid is accessed and used for exciting various target circuitry within the device by exciting the part of the grid that corresponds to the portion of the target circuitry to which access is desired.

Probe grid for integrated circuit excitation

A system for determining the endpoint associated with removing silicon from the backside of a flip chip type die includes a tool for removing silicon and a light source for directing light to the backside of the die. An electrical measuring apparatus, such as a voltmeter, ammeter or oscilloscope, is attached across the output pins of a package to which the die is attached. The light or ions directed toward the backside of the die induce a current in the devices formed in the semiconductor. The value of the current or voltage output depends on the thickness of material between the endpoint on the backside of the die and the devices in the epitaxial layer of the die. The induced signal can be monitored to determine the thickness. Silicon can be removed globally until the thickness is reasonable such that a local thinning tool can be used to remove silicon to get to the area of interest in a reasonable amount of time. The induced current can be monitored during local thinning. A viewing mechanism such as infrared microscopy can be used to locate the specific device or devices of interest in the epitaxial layer of the die. The viewing mechanism is also used to determine where localized thinning will occur.

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De Valle, TX, United States of America

Glen P Gilfeather