International Business Machines Corporation

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Glen L Miles

Arne Watson Ballantine

Jeffrey D Gilbert

Lawrence Alfred Clevenger

Kevin K Chan

Cyril Cabral, Jr

Randy William Mann

James J Quinlivan

Beth A Ward

Samuel C Ramac

Michael B Rice

Kevin M Houlihan

Francois M d'Heurle

Katherine Lynn Saenger

Yun-Yu Wang

James Spiros Nakos

Kwong Hon Wong

Anthony Gene Domenicucci

James M Harper

Lynne Marie Gignac

Ronnen Andrew Roy

Patrick William Dehaven

Horatio Seymour Wildman

Donna Kaye Johnson

Prabhat Tiwari

Anthony K Stamper

Chung H Lam

James William Adkisson

Kirk David Peterson

Jeffrey Bowman Johnson

Edmund Juris Sprogis

Robert K Leidy

Paul Charles Jamison

Peter James Lindgren

Nicky C Lu

John Anthony Bracchitta

Peter John Geiss

Shwu-Jen Jeng

Tina Jane Wagner

James McKell Edwin Harper

Rick L Mohler

Brian J Machesney

Robb Allen Johnson

Christa Regina Willets

James J Toomey

Donald Walter Rakowski

David C Mosher

Matthew D Gallagher

Frank Grellner

Chung-Yu Ting

Jame Spiros Nakos

Donald R Dean, Jr

Emmanuel Batt

Stephen D Warley

A portion of an IC layout that includes a plurality of through silicon vias (TSVs) is evaluated to identify linearly aligned TSVs. The portion of the IC layout is modified to reduce a number of the linearly aligned TSVs, resulting in less wafer breakage.

Arranging through silicon vias in IC layout

Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting CMOS transistor may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size may be directed to maximize dopant activation in the polysilicon near the gate dielectric and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. A region of polycrystalline silicon may have a varying grain size as a function of a distance measured from a surface of the dielectric film.

CMOS transistor with a polysilicon gate electrode having varying grain size

Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size

A process of forming a nitride film on a semiconductor substrate including exposing a surface of the substrate to a rapid thermal process to form the nitride film.

Structure and method for formation of a blocked silicide resistor

A process for forming a conductive contact having a flat interface. A layer containing niobium and titanium is deposited on a silicon substrate and the resulting structure is annealed in a nitrogen-containing atmosphere at about 500&deg; C. to about 700&deg; C. By this process, a flatter interface between silicide and silicon, which is less likely to cause junction leakage, is formed on annealing. The step of annealing also produces a more uniform bilayer, which is a better barrier against tungsten encroachment during subsequent tungsten deposition. Larger silicide grains are also formed so that fewer grain boundaries are produced, reducing metal diffusion in grain boundaries. The process can be used to form contacts for very small devices and shallow junctions, such as are required for current and future semiconductor devices.

Process for manufacturing a contact barrier

A method for adjusting an etch rate of a nitride layer, in accordance with the present invention includes, in a reaction chamber, providing a surface for depositing a nitride layer. The nitride layer is deposited on the surface by adjusting processing parameters to control an etch rate achievable for the nitride layer. The etch rate achievable results from the depositing step such that an ability to etch the nitride layer is determined by the adjustment of the process parameters. A refractive index measurement may be provided for monitoring the achievable etch rate for the nitride layer.

Modification of the wet characteristics of deposited layers and in-line control

A method of measuring temperature of momentary anneals in the temperature range of around 900&deg; C. is disclosed. The method comprises the steps of providing a substrate of doped polysilicon or single crystal silicon, applying a blocking layer on a portion of the substrate, selectively forming silicide on the substrate adjacent opposite ends of the blocking layer to define a resistor, subjecting the resistor to a momentary anneal in the temperature range around 900&deg; C., and measuring interfacial resistance between the silicide and the substrate after the annealing step, the resistance correlating to anneal temperature.

Method for temperature measurement using dopant segregation into titanium silicide

A semiconductor structure comprising a plurality of gates located on a semiconductor substrate; wherein insulating spacer is provided on sidewalls of the gates; and metallic silicide located between the gates is provided along with a method for its fabrication. A partially disposable spacer permits increased area for silicide formation without degrading the device short channel behavior.

Semiconductor structure having reduced silicide resistance between closely spaced gates and method of fabrication

Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900&deg; C., and more preferably between about 600-700&deg; C.

Low temperature formation of low resistivity titanium silicide

A logic chip including a non-volatile random access memory (NVRAM) array and method of fabrication thereof. The chip includes devices with gates on one or more of three polysilicon layers. Chip logic uses normal FETs and array support includes high voltage FETs. Both logic and support are CMOS. The gates of normal FETs in the chip logic are from the third, uppermost polysilicon layer. The third poly silicon layer also is used as a mask for high voltage FETs and array word lines, both of which use the second polysilicon layer for gates. The first polysilicon layer is used solely for cell floating gates.

Triple polysilicon embedded NVRAM cell and method thereof

Floating gates with field enhancement features are produced by a technique that makes possible structures smaller than the lithographically defined image. The floating gates produced having sharp tips for source-side injection flash memory cells. Moreover, the process provides an insulator cap over the floating gate that is self-aligned.

Fabricating a floating gate with field enhancement feature self-aligned

Recessing the floating gate of a NVRAM cell within a substrate or semiconductor layer between isolation structures permits manufacture by a simplified self-aligned process of high yield and economy while supporting maximum integration density and reducing or eliminating severe topography of the control gate connections which are formed in strips having a generally planar lower surface and which are of improved robustness and potentially fine pitch. Impurity implants are facilitated by thicknesses of various material present during portions of the process and in various combinations which may be advantageously exploited to obtain tailoring of impurity concentrations and profiles of both NVRAM cells and damascene field effect transistors formed by similar and compatible processes.

Damascene NVRAM cell and method of manufacture

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Essex Junction, VT, United States of America

Glen L Miles