Motorola Corporation

Glen D Caby

Nicholas J Spence

Gary W Hoshizaki

Jerome A Grula

Robert A Fuller

A data analyzer for use in BIST circuitry has been provided. The data analyzer allows both comparison analysis and signature analysis to be performed on a circuit response data stream. The data analyzer includes a plurality of data registers which are serially-coupled and where each data register is capable of performing comparison analysis and signature analysis on one data bit of the circuit response data stream. This allows the circuit under test can be completely and thoroughly tested for faults.

Enhanced data analyzer for use in bist circuitry

A built-in self test (BIST) circuit verifies the operation of a circuit under test in an integrated circuit. The BIST generates a series of test vectors with linear feedback shift register (LFSR) and applies the test vectors to the circuit under test. The output signal from the circuit under test in response to the test vectors is routed back and accumulating in a predetermined manner in the LFSR for providing a test signature. Thus, the same components in the LFSR generating the test vector also perform the accumulation of the test signature. The accumulating test signature may be used as a subsequent test vector.

Combinational data generator and analyzer for built-in self test

A configurable decode circuit for decoding in a block architected SRAM. The configurable decode circuit comprising a decode circuit (10) which decodes through a process of deselection, a first buffer circuit (12) for buffering decode circuit (10), a delayed clock signal (15) for enabling first buffer circuit (12), a gated transmission means (13) for decoupling first buffer circuit from second buffer circuit (14), second buffer circuit (14) for driving capacitive loads, and a means for delaying driver output (16) for enabling gated transmission means (13). The decode circuit (10) is built for simplifying synthesis of the layout of a configurable decode circuit for varying configurations. The configurable decode optimizes performance by reducing the number of circuits in the critical delay path and minimizing capacitive loading on internal circuit nodes.

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Tempe, AZ, United States of America

Glen D Caby