Sgs Microelettronica Spa

Giulio Iannuzzi

Giorgio De Santi

Livio Baldi

Claudio Contiero

Giuseppe Corda

Danilo Re

Fabrizio Andreani

Structure and method for metallization patterns of different thicknesses on a semiconductor device or integrated circuit. The improved structure and method utilizes three layers of metal in order to reduce the required number of processing steps. One preferred embodiment entails a single metal deposition sequence followed by two etch steps, while a second embodiment, suitable for thicker metallization, requires only two depositions and two etch steps.

Process for forming semiconductor device having multi-thickness

The method provides for the formation of a layer of metal silicide on the gate layer of polycrystalline silicon and, for each transistor of the CMOS pair, the simultaneous doping of the active regions and the gate polycrystalline silicon. In the structure produced by this method, the gate electrodes are of polycrystalline silicon covered by metal silicide and the gate electrode of the n-channel transistor is doped with n-type material, while the gate electrode of the p-channel transistor is doped with p-type impurities. This enables the production of low threshold voltages for both transistors even in the case of very high integration densities.

Fabricating a CMOS transistor having low threshold voltages using

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Vimercate, Italy

Giulio Iannuzzi