Texas Instruments Corporation

Other

Gishi Chung

William R McKee

Clarence W Teng

Randy McKee

Bing-Whey Shen

Lionel S White, Jr

William F Richardson

Dirk N Anderson

Duane E Carter

Donald J Coleman, Jr

Masaaki Yashiro

Fred D Fishburn

Kiyoshi Shirai

A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. Trenches are etched into a face of a body of semiconductor material. Storage nodes surrounding the trenches are created. A polysilicon layer is formed on the trench walls. A storage dielectric layer is formed on the trench walls, adjacent to the layer of polysilicon on the trench walls, so that the layer of polysilicon on the trench walls lies between the storage dielectric layer and the storage node. The layer of polysilicon on the trench walls reduces leakage current from the storage node. A trench type field plate isolated random access memory cell structure is also disclosed.

Dynamic memory storage capacitor having reduced gated diode leakage

A method is disclosed for preventing formation of undesirable polysilicon word line gate filaments in integrated circuit devices such as VLSI dynamic random access memories employing field plate isolation. Before the word lines are processed, an oxide layer is formed in the field plate openings beneath sidewalls of nitride along the edges of the field plate openings. The oxide layer partially fills an undercut area beneath a dip out of the sidewall of nitride. The dip out of the sidewall of nitride is removed. The removal of the dip out and the partial filling of the undercut area reduces the possibility of polysilicon word line filaments from forming around the edge of the field plate openings in the undercut area when the word lines are later added. A field plate isolated memory device is also disclosed wherein along the edges of the field plate openings, the partially filling oxide layer and the sidewall nitride layer are approximately coincident.

Method to eliminate gate filaments on field plate isolated devices

By placing boundary cells within areas of discontinuity of a memory array, such as in word line strap areas, stress on edge cells of the memory array is reduced; the reduction of stress improves leakage characteristics and pause-refresh capabilities of edge cells. The boundary cells may further be laid out in the areas of discontinuity with the same pattern as the memory array. Some of the boundary cells may be electrically biased to act as minority carrier sinks. By collecting minority carriers that otherwise may be attracted to edge cells of the memory array, the leakage characteristics of the edge cells and their pause-refresh capabilities are further enhanced. The boundary cells are particularly useful in improving leakage characteristics of dynamic random access memory devices of the trench capacitor type.

Boundary cells for improving retention time in memory devices

Poly sidewall process to reduce gated diode leakage

A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. The storage node of the capacitor is formed by placing a storage node material, such as implanted arsenic, into the trench walls of the device at a first tilt and a second tilt. The angle of the second tilt is preferably larger, higher, than the angle of the first tilt. This higher angle provides the storage node with a larger concentration of doping around the upper portion the trench walls. This larger concentration of doping reduces the charge leaking from the upper portion of the storage node into the substrate of semiconductor material. A trench type storage capacitor for a dynamic random access memory device is also disclosed.

High angle implant around top of trench to reduce gated diode leakage

The described embodiments of the present invention provide DRAM cells, structures and manufacturing methods. A DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. The transfer transistor is formed using a field plate isolation structure which includes a self-aligned moat area for the transfer transistor. The moat area slightly overlaps the capacitor area and allows for increased misalignment tolerance thus foregoing the requirement for misalignment tolerances built into the layout of the DRAM cell. The field plate itself is etched so that it has sloped sidewalls to avoid the formation of conductive filaments from subsequent conductive layers formed on the integrated circuit. The use of a self-aligned bitline contact between two memory cells alows for the elimination of alignment tolerances between the bitline contact and the gates of the transfer transistor of the memory cells.

Method for fabricating a trench DRAM

The described embodiments of the present invention provide DRAM cells, structures and manufaturing methods. In a first embodiment, a DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. The transfer transistor is formed using a field plate isolation structure which includes a self-aligned moat area for the transfer transistor. The moat area slightly overlaps the capacitor area and allows for increased misalignment tolerance thus foregoing the requirement for misalignment tolerances built into the layout of the DRAM cell. The field plate itself is etched so that it has sloped sidewalls to avoid the formation of conductive filaments from subsequent conductive layers formed on the integrated circuit. The use of a self-aligned bitline contact between two memory cells allows for the elimination of alignment tolerances between the bitline contact and the gates of the transfer transistors of the memory cells.

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Garland, TX, United States of America

Gishi Chung