Infineon Technologies Ag

International Business Machines Corporation

Other

Qimonda Ag

Altis Semiconductor, Snc

Altis Semiconductor

Gill Yong Lee

Daniel C Edelstein

Richard Anthony Conti

Kia-Seng Low

Prakash Chimanlal Dev

Chanro Park

David M Dobuzinsky

Scott David Halle

Alexander William Simpson

Peter Wrschka

Padraic C Shafer

Ramachandra Divakaruni

Timothy Joseph Dalton

Eugene John O'Sullivan

Ravikumar Ramachandran

Rainer Leuschner

Jochen C Beintner

Hiroyuki Akatsu

William J Cote

Ulrich Karl Klostermann

Xian Jay Ning

Arpan Pravin Mahorowala

Gregory Costrini

Rajiv M Ranade

Daniel Braun

Joachim Nuetzel

Philippe Blanchard

Faiz Dahmani

Frank Findeis

Woosik Kim

According to one embodiment of the present invention, a memory device includes a composite structure including a resistivity changing layer and an electrode layer being arranged on or above the resistivity changing layer. The resistivity changing memory device further includes a protection layer being arranged on or above the composite structure, the protection layer protecting the electrode layer against electromagnetic waves.

Integrated circuit, resistivity changing memory device, memory module, and method of fabricating an integrated circuit

A method for manufacturing an integrated circuit having a magnetic tunnel junction device is disclosed. The method includes depositing a bottom pinning structure above the bottom conductive structure. A first ferromagnetic structure is deposited above the bottom pinning structure in a chamber. A tunnel barrier structure is deposited above the first ferromagnetic layer structure in the chamber, and a second ferromagnetic structure is deposited above the tunnel barrier structure of the magnetic tunnel junction device in another chamber.

Method of forming integrated circuit having a magnetic tunnel junction device

Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices, wherein the second magnetic layer or free layer of a magnetic stack may be patterned using a wet etch technique. A cap layer is formed over the free layer after the free layer is patterned. The cap layer is formed using lift-off techniques. To form the cap layer, resist layers are deposited and patterned, and material layers are deposited over the resist layers. Portions of the material layers are removed when the resist is stripped.

MTJ patterning using free layer wet etching and lift off techniques

A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.

Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications

A magnetoresistive or magnetic memory element and a magnetic random access memory having one or more magnetic memory elements. The memory element includes a magnetic tunnel junction including first and a second magnetic layers. The first magnetic layer having a free magnetization. The free magnetization of the first magnetic layer is magnetically coupled to a first current line and a second current line for switching the free magnetization, and a mechanism for applying a static magnetic offset field in the direction of at least one of the first and second current lines.

Magnetic memory with static magnetic offset field

Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices that avoid shorting magnetic memory cells to upper levels of conductive lines during etching processes. One method involves using a hard mask having two material layers to pattern the lower magnetic material layers of an MTJ. The first material of the hard mask is thin and comprises an etch-resistant material. The second material of the hard mask deposited over the first material is thicker and is less etch-resistant than the first material. At least a portion of the second material is sacrificially removed during the etch process of the lower magnetic material layers. A conformal or non-conformal material may be used as the second material of the hard mask. The hard mask used to pattern lower magnetic materials of an MTJ may comprise a single layer of non-conformal material.

Mask schemes for patterning magnetic tunnel junctions

A method of manufacturing a resistive semiconductor memory device (), comprising depositing an insulating layer () over a workpiece (), and defining a pattern for a plurality of alignment marks () and a plurality of conductive lines () within the insulating layer (). A conductive material is deposited over the wafer to fill the alignment mark () and conductive line () patterns. The insulating layer () top surface is chemically-mechanically polished to remove excess conductive material from the insulating layer () and form conductive lines (), while leaving conductive material remaining within the alignment marks (). A masking layer () is formed over the conductive lines (), and at least a portion of the conductive material is removed from within the alignment marks (). The alignment marks () are used for alignment of subsequently deposited layers of the resistive memory device ().

MRAM MTJ stack to conductive line alignment method

A method of patterning a bottom electrode for a magnetic memory cell. The bottom electrode is patterned prior to the deposition of the soft layer of the magnetic tunnel junction (MTJ) material stack, preventing the formation of fencing on the sidewalls of the soft layer, which can cause shorts to subsequently formed conductive lines of the magnetic memory device. A sacrificial mask is used to pattern the bottom electrode material, and at least a portion of the sacrificial mask is consumed or removed during the patterning of the bottom electrode material. The soft layer is then deposited and patterned using a hard mask.

Method of patterning a magnetic memory cell bottom electrode before magnetic stack deposition

A method of fabricating a magnetic memory device and a magnetic memory device structure. A buffer insulating layer is deposited over the top surface of the conductive hard mask of a magnetic memory cell. The buffer insulating layer is left remaining over the conductive hard mask top surface while the various material layers of the device are patterned and etched. The buffer insulating layer prevents the conductive hard mask top surface from being damaged during plasma-containing processes.

Integration scheme for avoiding plasma damage in MRAM technology

A method of fabricating a magnetic memory cell and an MRAM structure. A thin conductive hard is used to pattern a magnetic stack material layer. Conductive studs are fully landed on the top of the thin conductive hard mask, preventing the magnetic memory cells from being exposed subsequent etchant chemistries. The conductive studs provide a large process window for the upper level wiring trench formation, and also provide etch selectivity during the patterning of the upper level wiring.

Subtractive stud formation for MRAM manufacturing

A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.

Carbon-graded layer for improved adhesion of low-k dielectrics to silicon substrates

A material that is harder than silicon dioxide is used as a hard mask to pattern the soft layer of an MTJ stack of a magnetic memory device, which increases the process window for post-MTJ stack planarization. The soft layer hard mask material may comprise SiC, SiON, SiCN or SiN or another dielectric material having a Young's modulus greater than the Young's modulus of silicon dioxide. A hard fill dielectric material is also used as an insulating material over the hard mask used to pattern the soft layer. The fill dielectric material may also comprise SiC, SiON, SiCN or SiN or another dielectric material having a Young's modulus greater than the Young's modulus of silicon dioxide.

Magnetic tunnel junction patterning using SiC or SiN

A process for forming a damascene structure includes depositing a bilayer comprising a first dielectric layer and a second dielectric layer onto a substrate, wherein the first layer has a dielectric constant higher than the second layer, and wherein the second layer is selected from a low k dielectric material comprising Si, C, O and H. The multi-step damascene structure is patterned into the dielectric bilayer using highly selective anisotropic reactive ion etching. Photoresist, polymers and post etch residues are removed from the substrate using a plasma ashing process without damaging the underlying dielectric layers.

Process for forming a damascene structure

In accordance with the present invention, a method for employing and removing inorganic anti-reflection coatings, includes the steps of providing a first dielectric layer on a semiconductor device structure to be processed, the first dielectric layer being selectively removable relative to the semiconductor device structure, and forming an inorganic dielectric anti-reflection coating (DARC) on the first dielectric layer, the DARC being selectively removable relative to the first dielectric layer. A resist layer is patterned on the DARC. The resist is selectively removable relative to the DARC. The semiconductor device structure is etched, and the resist layer, the DARC and the first dielectric layer are selectively removed.

Growing community of inventors

Wappingers Falls, NY, United States of America

Gill Yong Lee