Samsung Electronics Co., Ltd.

Gil-Heyun Choi

Byung-Hee Kim

Jong-Myeong Lee

Myoung-Bum Lee

Hyun-seok Lim

Sang-Bom Kang

Hee-Sook Park

Hyun-Su Kim

Sug-Woo Jung

Jong-ho Yun

Eun-ji Jung

In-sang Jeon

Jong-Ho Lee

Sang-in Lee

Kwang-Jin Moon

Kyung-In Choi

Dong-Chan Lim

Byung-Hak Lee

Sang-bum Kang

A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug.

Stacked semiconductor device and method of fabrication

Semiconductor devices and methods of fabricating the same are provided. A gate insulating film is provided on a semiconductor substrate. A polymetal gate electrode is provided on the gate insulating film. The polymetal gate electrode includes a conductive polysilicon film on the gate insulating film, a first metal silicide film on the conductive polysilicon film, a barrier film on the first metal silicide film, and a metal film on the barrier film. The barrier film includes a titanium nitride (TiN) film on the first metal silicide film and a buffer layer between the TiN film and the metal film.

Semiconductor devices having polymetal gate electrodes

Semiconductor device including upper and lower transistors and interconnection between upper and lower transistors

After a processing chamber is used to deposit a refractory metal film on a substrate, the chamber is plasma-treated with a gas including either nitrogen and/or hydrogen and in-situ cleaned. By plasma-treating the chamber with a gas including nitrogen, the refractory metal film that forms on interior surfaces of the chamber during substrate processing is nitrided. The nitrided refractory metal film can be removed from the chamber during the in-situ cleaning. By plasma-treating the chamber with a gas including hydrogen, reaction by-products generated in the chamber is diluted removed. The chamber may be plasma-treated in a gas ambient including both nitrogen and hydrogen. Also, the plasma treatment may be performed before and after the in-situ cleaning.

Method of cleaning a chemical vapor deposition chamber

A method for forming a dual gate includes providing a semiconductor substrate that has a first region of a first conductivity type and a second region of a second conductivity type. A gate insulating layer is formed on the semiconductor substrate. An initial metal nitride layer is formed on the gate insulating layer, opposite to the semiconductor substrate. Nitrogen ions are implanted into the initial metal nitride layer in the second transistor region to form a nitrogen-rich metal nitride layer. The initial metal nitride layer is patterned to form a first gate electrode in the first region. The nitrogen-rich metal nitride layer is patterned to form a second gate electrode in the second region. The work function of the nitrogen-rich metal nitride layer is higher than that of the initial metal nitride layer.

Methods of forming dual gate semiconductor devices having a metal nitride layer

A method of fabricating a semiconductor device having a recess region in an insulation layer on a silicon substrate, comprising the steps of depositing a barrier metal over the entire surface of the insulation layer including the substrate surface in the recess region, depositing selectively an anti-nucleation layer on the barrier metal except in the recess region, depositing a CVD-Al layer on the barrier metal in the recess region, depositing a metal or a metal alloy inhibiting aluminum migration on the anti-nucleation layer and the barrier metal except in the recess region, and depositing a PVD-Al layer and re-flowing the PVD-Al layer, for improving the quality of aluminum grooves. The present method inhibits PVD-Al migration and grain growth, which results in preventing abnormal patterning in the semiconductor device.

Method of fabricating metal lines in a semiconductor device

A semiconductor device fabrication method having a recess region in an insulation layer on a silicon substrate, includes the steps of depositing a barrier metal on an entire surface of the insulation layer, filling the recess region with an oxide layer, removing the barrier metal on an upper side of the insulation layer, removing the oxide layer in the recess region and exposing the barrier metal of the recess region, depositing a CVD-Al layer on the barrier metal, and depositing a PVD-Al layer on the CVD-Al layer and re-flowing the PVD-Al layer. The fabrication method of a semiconductor integrated circuit according to the present invention selectively removes a barrier metal in the outside of the recess region to expose the insulation layer to the air, and deposits the CVD-Al layer and the PVD-Al layer, which results in controlling abnormal growth of the CVD-Al metal.

Semiconductor device fabrication method for filling high aspect ratio openings in insulators with aluminum

A method is provided for forming a metal wiring layer of a semiconductor device, which is performed in an airtight space, the pressure of which is maintained below atmospheric pressure, to form a metal deposition prevention layer. An interlayer dielectric layer pattern is formed on a semiconductor substrate so as to define a hole region. A metal film is formed on the top surface of the interlayer dielectric layer pattern under a vacuum state so as to expose the side walls of the hole region. The metal layer is oxidized in the airtight space, the pressure of which is maintained below atmospheric pressure in an oxygen atmosphere, thereby forming a metal deposition prevention layer. A metal liner is selectively formed at the side walls of the hole region. A metal layer is formed inside the hole region defined by the metal liner and on the metal deposition prevention layer. The metal liner is heat-treated and reflowed.

Method of selectively depositing a metal layer in an opening in a dielectric layer by forming a metal-deposition-prevention layer around the opening of the dielectric layer

A method of manufacturing a barrier metal layer uses atomic layer deposition (ALD) as the mechanism for depositing the barrier metal. The method includes supplying a first source gas onto the entire surface of a semiconductor substrate in the form of a pulse, and supplying a second source gas, which reacts with the first source gas, onto the entire surface of the semiconductor substrate in the form of a pulse. In a first embodiment, the pulses overlap in time so that the second source gas reacts with part of the first source gas physically adsorbed at the surface of the semiconductor substrate to thereby form part of the barrier metal layer by chemical vapor deposition whereas another part of the second source gas reacts with the first source gas chemically adsorbed at the surface of the semiconductor substrate to thereby form part of the barrier metal layer by atomic layer deposition. Thus, the deposition rate is greater than if the barrier metal layer were only formed by ALD. In the second embodiment, an impurity-removing gas is used to remove impurities in the barrier metal layer. Thus, even if the gas supply scheme is set up to only use ALD in creating the barrier metal layer, the deposition rate can be increased without the usual accompanying increase in the impurity content of the barrier metal layer.

Method of manufacturing a barrier metal layer using atomic layer deposition

A method for forming a metal interconnection filling a contact hole or a groove having a high aspect ratio, and a contact structure fabricated thereby. An interdielectric layer pattern, having a recessed region serving as a contact hole, a via hole or a groove, is formed on a semiconductor substrate. A barrier metal layer is formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed. An anti-nucleation layer is selectively formed only on the non-recessed region of the barrier metal layer. The anti-nucleation layer is formed by forming a metal layer overlying the barrier metal layer in regions other than the recessed region, and then spontaneously oxidizing the metal layer in a vacuum. Also, the anti-nucleation layer may be formed by in-situ forming the barrier metal layer and the metal layer and then oxidizing the metal layer by an annealing process. Subsequently, a metal plug is selectively formed in the recessed region, surrounded by the barrier metal layer, thereby forming a metal interconnection for completely filling the contact hole or the groove having a high aspect ratio. A metal liner may be formed instead of the metal plug, followed by forming a metal layer filling the region surrounded by the metal liner, thereby forming a metal interconnection for completely filling the contact hole or groove having a high aspect ratio.

Method for forming metal interconnection in semiconductor device and interconnection structure fabricated thereby

A method of forming a metal nitride film using chemical vapor deposition (CVD), and a method of forming a metal contact and a semiconductor capacitor of a semiconductor device using the same, are provided. The method of forming a metal nitride film using chemical vapor deposition (CVD) in which a metal source and a nitrogen source are used as a precursor, includes the steps of inserting a semiconductor substrate into a deposition chamber, flowing the metal source into the deposition chamber, removing the metal source remaining in the deposition chamber by cutting off the inflow of the metal source and flowing a purge gas into the deposition chamber, cutting off the purge gas and flowing the nitrogen source into the deposition chamber to react with the metal source adsorbed on the semiconductor substrate, and removing the nitrogen source remaining in the deposition chamber by cutting off the inflow of the nitrogen source and flowing the purge gas into the deposition chamber. Accordingly, the metal nitride film having low resistivity and a low content of Cl even with excellent step coverage can be formed at a temperature of 500&deg; C. or lower, and a semiconductor capacitor having excellent leakage current characteristics can be manufactured. Also, a deposition speed, approximately 20 A/cycle, is suitable for mass production.

Method of forming metal nitride film by chemical vapor deposition and method of forming metal contact and capacitor of semiconductor device using the same

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Sungnam, South Korea

Gil-Heyun Choi