Samsung Electronics Co., Ltd.

Gil-heyun Choi

Byung-Hee Kim

Byung-Lyul Park

Hee-Sook Park

Jong-myeong Lee

Hyun-Su Kim

Sang-Woo Lee

Sang-Bom Kang

Kyung-In Choi

Jong-Myeong Lee

Jong-Ho Yun

Byung-Hak Lee

Jae-Hwa Park

Kwang-jin Moon

Pil-Kyu Kang

Eun-Ji Jung

Dong-chan Lim

Sug-Woo Jung

Kwang-Jin Moon

Deok-Young Jung

Woong-Hee Sohn

Sang-Hoon Ahn

Jang-Hee Lee

Dae-lok Bae

Chang-Won Lee

Jin-ho Park

Jong-Won Hong

Woong-hee Sohn

Seong-hwee Cheong

Sun-Pil Youn

Jong-Min Baek

Ji-soon Park

Suk-chul Bang

Seong-Geon Park

You-Kyoung Lee

Tae-Ho Cha

Ju-young Yun

Kyu-Hee Han

Jong-Ryeol Yoo

Dong-Chan Lim

Su-Kyoung Kim

Sang-Don Nam

Do-Sun Lee

Byeong-jun Kim

Sang-bum Kang

Hyun-Soo Chung

In-Sun Park

Chang-won Lee

Eunkee Hong

Eun-Ok Lee

Kyoung-Hee Kim

Hyun-Bae Lee

Geum-jung Seong

Kun-sang Park

Ho-Ki Lee

Hei-seung Kim

Jong-ho Yun

Eun-ji Jung

Jin-Ho Park

Ho-jin Lee

Sang-in Lee

Hyeon-Deok Lee

Woo-Jin Lee

Myoung-Bum Lee

Dae-Yong Kim

Kyu-ha Lee

Hyun-seok Lim

Jin-ho Chun

Seung-man Choi

Ha-Young Yi

Hyo-Jong Lee

Myoung Seok Lee

Son-kwan Hwang

Kyung-Mun Byun

Byung-Iyul Park

Seung-Hwan Lee

Sung-Man Kim

Si-Young Choi

Youngseok Kim

Min-sang Song

Bo-Young Lee

Yun-Jung Lee

Ja-hum Ku

Seung-Woo Shin

Rak-Hwan Kim

Tae-Yeong Kim

Jeong-Tae Kim

Jun-Won Lee

Jun-ho Park

Seong-Jun Heo

Ju-seon Goo

Seong-min Son

Jae-woo Kim

Hong-Rae Kim

Hong-Gun Kim

Dong-Kak Lee

Jong-Wan Choi

Jung-Hun Seo

Kwan-Jong Roh

In-Sang Jeon

A capacitor structure includes a substrate including an electrode pad and a ground pad, a plurality of dielectric layers on the substrate, the plurality of dielectric layers being at different levels on the substrate, a plurality of conductive pattern layers in at least two dielectric layers of the plurality of dielectric layers, the at least two dielectric layers of the plurality of dielectric layers being first dielectric layers, a plurality of via plugs connecting the plurality of conductive pattern layers to each other, and at least one contact layer in at least one second dielectric layer of the plurality of dielectric layers, the at least one second dielectric layer being different from the at least two first dielectric layers, and the at least one contact layer electrically connecting the plurality of conductive pattern layers to the electrode pad and the ground pad.

Capacitor structure and semiconductor device including the same

A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure.

Semiconductor device and method of fabricating the same

A semiconductor device includes a substrate, a conductive pattern, a side spacer, and an air gap. The substrate includes an interlayer insulating layer and a trench penetrating the interlayer insulating layer. The conductive pattern is disposed within the trench of the substrate. The side spacer is disposed within the trench. The side spacer covers an upper side surface of the conductive pattern. The air gap is disposed within the trench. The air gap is bounded by a sidewall of the trench, the side spacer, and a lower side surface of the conductive pattern. A level of a bottom surface of the conductive pattern is lower than a level of bottom surfaces of the side spacer.

A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.

Semiconductor chips having through silicon vias and related fabrication methods and semiconductor packages

A semiconductor device includes a via structure having a top surface with a planar portion and a protrusion portion that is surrounded by the planar portion, and includes a conductive structure including a plurality of conductive lines contacting at least a part of the top surface of the via structure.

An integrated circuit device including a through-silicon-via (TSV) structure and methods of manufacturing the same are provided. The integrated circuit device may include the TSV structure penetrating through a semiconductor structure. The TSV structure may include a first through electrode unit including impurities of a first concentration and a second through electrode unit including impurities of a second concentration greater than the first concentration.

Integrated circuit device having through-silicon-via structure

Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer.

Semiconductor device including through via structures and redistribution structures

The inventive concept provides porous, low-k dielectric materials and methods of manufacturing and using the same. In some embodiments, porous, low-k dielectric materials are manufactured by forming a porogen-containing dielectric layer on a substrate and then removing at least a portion of said porogen from the layer.

Method of manufacturing a semiconductor device having a porous, low-k dielectric layer

Semiconductor devices having an optical transceiver include a cladding on a substrate, a protrusion vertically extending trough the cladding and materially in continuity with the substrate, and a coupler on the cladding and the protrusion.

Semiconductor devices having optical transceiver

A semiconductor device includes a circuit pattern over a first surface of a substrate, an insulating interlayer covering the circuit pattern, a TSV structure filling a via hole through the insulating interlayer and the substrate, an insulation layer structure on an inner wall of the via hole and on a top surface of the insulating interlayer, a buffer layer on the TSV structure and the insulation layer structure, a conductive structure through the insulation layer structure and a portion of the insulating interlayer to be electrically connected to the circuit pattern, a contact pad onto a bottom of the TSV structure, and a protective layer structure on a second surface the substrate to surround the contact pad.

Integrated circuit having through silicon via structure with minimized deterioration

A semiconductor device can include an insulation layer on that is on a substrate on which a plurality of lower conductive structures are formed, where the insulation layer has an opening. A barrier layer is on a sidewall and a bottom of the opening of the insulation layer, where the barrier layer includes a first barrier layer in which a constituent of a first deoxidizing material is richer than a metal material in the first barrier layer and a second barrier layer in which a metal material in the second barrier layer is richer than a constituent of a second deoxidizing material. An interconnection is in the opening of which the sidewall and the bottom are covered with the barrier layer, the interconnection is electrically connected to the lower conductive structure.

Semiconductor devices and methods of manufacturing the same

A semiconductor device including a lower layer, an insulating layer on a first side of the lower layer, an interconnection structure in the insulating layer, a via structure in the lower layer. The via structure protrudes into the insulating layer and the interconnection structure.

Via connection structures, semiconductor devices having the same, and methods of fabricating the structures and devices

An optical input/output (I/O) device is provided. The device includes a substrate including an upper trench; a waveguide disposed within the upper trench of the substrate; a photodetector disposed within the upper trench of the substrate and comprising a first end surface optically connected to an end surface of the waveguide; and a light-transmitting insulating layer interposed between the end surface of the waveguide and the first end surface of the photodetector.

Optical input/output device and method of fabricating the same

Growing community of inventors

Seoul, South Korea

Gil-heyun Choi