International Business Machines Corporation

Gie Lee

David James Hathaway

John Maxwell Cohn

Jeanne P Bickford

Jason D Hibbeler

Wayne Harvey Woods, Jr

Jeffrey G Hemmett

Ulrich Alfons Finkler

Fook-Luen Heng

Alan Weger

Kerry A Kravec

Wing L Lai

Sebnem Jaji

Cole E Zemke

Brian M Trapp

Thomas S Barnett

Rashmi D Chatty

William Y Chang

Methods for modeling a random variable with spatially inhomogenous statistical correlation versus distance, standard deviation, and mean by spatial interpolation with statistical corrections. The method includes assigning statistically independent random variable to a set of seed points in a coordinate frame and defining a plurality of test points at respective spatial locations in the coordinate frame. A equation for a random variable is determined for each of the test points by spatial interpolation from one or more of the random variable assigned to the seed points. The method further includes adjusting the equation of the random variable at each of the test point with respective correction factor equations.

Method of distributing a random variable using statistically correct spatial interpolation continuously with spatially inhomogeneous statistical correlation versus distance, standard deviation, and mean

A method of modeling yield for semiconductor products includes determining expected faults for each of a plurality of library elements by running a critical area analysis on each of the library elements, and assessing, from the critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products. Thereafter, the expected number of faults for each library element is updated in response to observed yield. A database is established, which includes the die size and expected faults for each of the library elements. Integrated circuit product die size is estimated, and library elements to be used to create the integrated circuit die are selected. Fault and size data for each of the selected library elements are obtained, the adjusted estimated faults for each of the library elements are summed, and estimated yield is calculated.

Equivalent gate count yield estimation for integrated circuit devices

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Gie Lee