Vantis Corporation

Lattice Semiconductor Corporation

Advanced Micro Devices Corporation

Giap H Tran

Om P Agrawal

Bradley A Sharpe-Geisler

Bai Yen Nguyen

Herman M Chang

Brad Sharpe-Geisler

Kiet Truong

Henry Law

Jack Tim Wong

Kuang Chi

Keith Truong

Ravi Lall

Siak Chon Kee

John D Tobey

In one embodiment, an integrated circuit has hot-socket circuitry to protect I/O drivers during hot-socket events. The hot-socket circuitry has (i) N-well-to-pad switcher circuitry that ties driver PMOS N-wells to pads when the pad voltages are greater than the power-supply voltage and (ii) N-well-to-power-supply switcher circuitry that ties the driver PMOS N-wells to the power supply when the pad voltages are less than the power-supply voltage. The hot-socket circuitry also has a special PMOS device connected between the pad and a gate of at least one other PMOS device in the N-well-to-power-supply switcher circuitry to turn off the N-well-to-power-supply switcher circuitry quickly whenever the pad voltage is greater than the power-supply voltage. Applying a reduced power-supply voltage level to the gate of the special PMOS device enables the hot-socket circuitry to be implemented without having to use low Vt devices and without having to implement substantially large drive strengths.

Hot-socket circuitry

In one integrated circuit embodiment, a programmable pull-down output buffer is calibrated by sequentially configuring the buffer at different drive-strength levels and adjusting a source current applied to the buffer until the voltage at an input node of the buffer reaches a reference voltage level. A programmable pull-up output buffer is then calibrated by sequentially configuring a pull-down output buffer based on the pull-down buffer calibration results and adjusting the drive-strength level of the pull-up buffer until the voltage at a common node between the two buffers reaches a reference voltage level. Average calibration results are generated by averaging multiple calibration results for each setting. Output buffers are thereby calibrated to compensate for PVT variations without using any external resistors and without requiring any I/O pins of the integrated circuit.

PVT compensation scheme for output buffers

Within a programmable logic device, a multi-data rate SDRAM interface such as a DDR SDRAM interface includes in one embodiment a DQS clock tree, a slave delay circuit, and a delay-locked loop (DLL). The slave delay circuit is adapted to shift the phase of the DQS signal relative to the phase of data to provide a phase-shifted DQS signal to the DQS clock tree, and the DLL is adapted to control the slave delay circuit. The DLL includes a delay line comprising a plurality of instantiations of the slave delay circuit and a plurality of facsimiles of the DQS clock tree.

Programmable logic device with a multi-data rate SDRAM interface

A programmable logic device (PLD) such as a field programmable gate array (FPGA) has a power-down mode of operation that reduces power consumption during standby or idle periods for the PLD. In one embodiment, the PLD includes a switch such as an internal power supply operable to provide power to the logic core of the PLD, such as the programmable logic blocks, routing structure, and volatile configuration memory. The internal power supply powers down the logic core in response to assertion of a power-down signal, while power is maintained to other circuitry of the PLD.

Programmable logic device with power-saving architecture

Systems and methods are disclosed herein to provide improved I/O techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a reference circuit adapted to receive a first reference signal and provide a second plurality of reference signals based on the first reference signal, with the reference circuit providing default voltage levels for the second plurality of reference signals if a first control signal is asserted. An input/output circuit, coupled to the reference circuit and to an output driver, receives the second plurality of reference signals to control the output driver to provide an output signal, with the output driver operated with the default voltage levels if the first control signal is asserted.

Input/output systems and methods

A programmable logic device (PLD) such as a field programmable gate array (FPGA) has a power-down mode of operation that reduces power consumption during standby or idle periods for the PLD. In one embodiment of the invention, the PLD includes an internal power supply operable to provide power to PLD's programmable logic blocks. The internal power supply powers down the programmable logic blocks in response to the assertion of a power-down signal.

Within a programmable logic device (PLD), a DDR SDRAM interface for a DDR SDRAM is provided, the DDR SDRAM providing data to the PLD on the rising and falling edges of a DQS signal, the interface including: a first register adapted to capture data associated with the falling edges of the DQS signal; a second register adapted to capture data associated with the rising edges of the DQS signal; and clock edge selection logic circuitry coupled to clock inputs of the first and second registers and adapted to select between the rising or falling clock edges of an internal PLD clock to clock the first and second registers and thereby transfer the captured data into core logic for the PLD, the selection of the clock edge based on a phase relationship between the internal PLD clock and the DQS signal.

Programmable logic device with a double data rate SDRAM interface

Systems and methods are disclosed to provide programmable input/output functionality for a programmable logic device. For example, in accordance with one embodiment of the present invention, a programmable interface selectively employs a scalable serializer-deserializer and clock and data recovery circuit. The programmable interface further includes programmable input/output buffers and embedded memory to allow the programmable logic device to support a wide range of input/output interface standards.

Scalable serializer-deserializer architecture and programmable interface

Programmable devices, such as FPGAs, are designed with I/O buffer architectures having (at least) three different types of I/O buffers: single-ended buffers with Peripheral Component Interconnect (PCI) clamps, single-ended buffers without PCI clamps, and differential buffers without PCI clamps. By distributing these different types of I/O buffers around the periphery of the device, a relatively low-cost device can be implemented with relatively small I/O buffers that collectively provide all of the I/O signaling functionality of prior-art devices that are implemented with relatively large, all-purpose I/O buffers, each of which supports the full range of I/O signaling options available on the device.

I/O buffer architecture for programmable devices

A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT's) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT's and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions. Each VGB has a common controls section, a wide-gating section and a carry-propagating section. Each super-VGB has a centrally-shared section of longline drivers that may be accessed from any of the constituent VGB's. A diversified spectrum of interconnect lines, including 2xL, 4xL, 8xL and direct connect surround each super-VGB to provide different kinds of interconnect.

Variable grain architecture for FPGA integrated circuits

Methods for configuring FPGA's having variable grain components for providing time-shared access to interconnect resources

A Variable Grain Architecture (VGA) device includes a shared output component (SOC) that may be used for programmably-routing process result signals onto either or plural ones of differently directed longlines within an FPGA. Plural VGB's make shared use of each SOC to output respective function signals to the longlines. The SOC may be also used for programmably-routing signals (e.g., feedthrough signals) that are selectively acquired from either one of equivalent but differently positioned interconnect channels. Such freedom in routing VGB result signals or feedthrough signals can allow FPGA configuring software to explore a wider range of partitioning, placement and/or routing options for finding optimized implementations in the VGA FPGA device of various, supplied design specifications.

Methods for configuring FPGA's having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources

A Variable Grain Architecture is disclosed wherein Variable Grain Blocks (VGB's) are wedged together in mirror opposition to one another to define super-VGB structures. The super-VGB structures are arranged as a matrix within an FPGA device. Each VGB includes progressive function synthesizing layers for forming more complex function signals by folding together less complex function signals of preceding layers. A function spawning layer containing a set of function spawning lookup tables (LUT's) is provided near the periphery of the corresponding super-VGB structure. In one case, the function spawning layer is L-shaped and includes a symmetrical distribution of Configurable Building Blocks. A signal-acquiring layer interfaces with adjacent interconnect lines to acquire input terms for the LUT's and controls. A decoding layer is interposed between the signal-acquiring layer and the function spawning layer for providing strapping and intercept functions. Each VGB has a common controls section, a wide-gating section and a carry-propagating section. Each super-VGB has a centrally-shared section of longline drivers that may be accessed from any of the constituent VGB's. A diversified spectrum of interconnect lines, including 2&times;L, 4&times;L, 8&times;L and direct connect surround each super-VGB to provide different kinds of interconnect.

A Variable Grain Architecture (VGA) includes a shared output component (SOC) that may be used for outputting different signals onto a shared longline within an FPGA. Plural VGB's make shared use of the SOC to out respective function signals to the shared longline.

Methods for configuring FPGA's having variable grain blocks and shared logic for providing time-shared access to interconnect resources

A Field Programmable Gate Array (FPGA) device includes a plurality of variable grain blocks (VGBs) and a plurality of interconnect lines for providing program-defined routing of signals between the VGBs. The VGBs include a plurality of L-organized CBBs (configurable logic blocks) having function-producing resources. Each CBB includes 6 term inputs, 2 control inputs and one direct connect output. Each CBB includes two configurable building elements having 3 term inputs and 1 control input, respectively. The plurality of interconnect lines includes a direct connect architecture for providing programmably-selectable, dedicated connections between a center VGB, in particular a CBB, and neighboring VGBs. The direct connect architecture and positioning of inputs and outputs enables 1) enhanced flexibility and efficiency in the configuration placement and routing software 2) efficiently emulates random logic nets and 3) reduces many direct connect line wire lengths.

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San Jose, CA, United States of America

Giap H Tran