Samsung Electronics Co., Ltd.

Gi-Gwan Park

Jung-Gun You

Yong-Suk Tak

Ki-il Kim

Dong-Suk Shin

Sug-Hyun Sung

Tae-young Kim

Bon-Young Koo

Ki-Yeon Park

Tae-Jong Lee

Myung-Yoon Um

Sung-soo Kim

Dong-Woo Kim

Jae-hoon Lee

Ha-Jin Lim

Koung-min Ryu

Sung-Hyun Choi

Dong-Chan Suh

Jae-Hoon Lee

Weon-hong Kim

Jae-yup Chung

Dong-Ho Cha

Tae-Won Ha

Dong-Hyuk Kim

Sang-koo Kang

Yongkuk Jeong

Won-Oh Seo

Jung-gun You

Sang-Su Kim

Cheol Kyu Kim

Jin-bum Kim

Dae-hee Kim

Young-Gun Ko

Yong-Ho Jeon

Hyung-Dong Kim

Ji-myoung Lee

Baik-Min Sung

Young-Mook Oh

Chong-Kwang Chang

Sun-ki Min

Myung-geun Song

Je-min Yoo

Ho-Sung Son

Jong-Han Lee

Hak-yoon Ahn

Song-E Kim

Hyun-seung Kim

Jeong-hyuk Yim

Sung-uk Jang

Yi-young Na

Ho-Jin Jeon

Kang-hun Moon

Mi-seon Park

Sang-yub Ie

Hye-ri Hong

A semiconductor device can include a field insulating film on a substrate and a fin-type pattern of a particular material, on the substrate, having a first sidewall and an opposing second sidewall. The fin-type pattern can include a first portion of the fin-type pattern that protrudes from an upper surface of the field insulating film and a second portion of the fin-type pattern disposed on the first portion. A third portion of the fin-type pattern can be disposed on the second portion where the third portion can be capped by a top rounded surface of the fin-type pattern and the first sidewall can have an undulated profile that spans the first, second and third portions.

Semiconductor device having fin-type pattern with varying widths along a center vertical line thereof

Methods for fabricating semiconductor devices include forming a fin-type pattern protruding on a substrate, forming a gate electrode intersecting the fin-type pattern, forming a first recess adjacent to the gate electrode and within the fin-type pattern by using dry etching, forming a second recess by treating a surface of the first recess with a surface treatment process including a deposit process and an etch process, and forming an epitaxial pattern in the second recess.

Method of fabricating semiconductor device

A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

Semiconductor device

A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.

Semiconductor device with a fin-shaped active region and a gate electrode

An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.

Fin field effect transistors having liners between device isolation layers and active areas of the device

A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgas sing prevention pattern sequentially stacked.

Semiconductor devices and methods of manufacturing the same

A semiconductor device capable of adjusting profiles of a gate electrode and a gate spacer by implanting or doping an element semiconductor material into an interlayer insulating layer may be provided. The semiconductor device may include a gate spacer on a substrate, the gate spacer defining a trench, a gate electrode filling the trench, and an interlayer insulating layer on the substrate, which surrounds the gate spacer, and at least a portion of which includes germanium.

Semiconductor device and method for fabricating the same

A material layer, a semiconductor device including the material layer, and methods of forming the material layer and the semiconductor device are provided herein. A method of forming a SiOCN material layer may include supplying a silicon source onto a substrate, supplying a carbon source onto the substrate, supplying an oxygen source onto the substrate, supplying a nitrogen source onto the substrate, and supplying hydrogen onto the substrate. When a material layer is formed according to a method of the present inventive concepts, a material layer having a high tolerance to wet etching and/or good electric characteristics may be formed, and may even be formed when the method is performed at a low temperature.

Material layers, semiconductor devices including the same, and methods of fabricating material layers and semiconductor devices

An integrated circuit (IC) device includes a pair of fin-shaped active areas that are adjacent to each other with a fin separation area therebetween, the pair of fin-shaped active areas extend in a line, and a fin separation insulating structure in the fin separation area, wherein the pair of fin-shaped active areas includes a first fin-shaped active area having a first corner defining part of the fin separation area, and wherein the fin separation insulating structure includes a lower insulating pattern that covers sidewalls of the pair of fin-shaped active areas, and an upper insulating pattern on the lower insulating pattern to cover at least part of the first corner, the upper insulating pattern having a top surface at a level higher than a top surface of each of the pair of fin-shaped active areas.

Integrated circuit device

A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate; a gate insulating film covering a top surface and both side walls of the fin-shaped active region; a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film; one pair of insulating spacers on both side walls of the gate electrode; and a source region and a drain region on the substrate and respectively located on sides of the gate electrode. The source region and the drain region form a source/drain pair. The one pair of insulating spacers include protrusions that protrude from upper portions of the one pair of insulating spacers toward the gate electrode.

Semiconductor device including gate having dents and spacer protrusions extending therein

Multigate metal-oxide semiconductor field effect transistor

Semiconductor device having a fin-shaped active region and a gate electrode

Growing community of inventors

Suwon-si, South Korea

Gi-Gwan Park