Advanced Micro Devices Corporation

Globalfoundries Inc.

Gert Burbach

Manfred Horstmann

Karsten Wieczorek

Andy C Wei

Peter Javorka

Rolf Stephan

Thomas Feudel

Jan Hoentschel

Hartmut Ruelke

Anthony Mowry

Ralf Van Bentum

Massud Aminpur

Carsten Hartig

Christian Zistl

Stephan Kruegel

Michael Raab

Markus Forsberg

Gotthard Jungnickel

Joe Bloomquist

Johannes Groschopf

David C Greenlaw

Frank Heinlein

By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.

Temperature monitoring in a semiconductor device by using a PN junction based on silicon/germanium materials

By selectively performing a pre-amorphization implantation process in logic areas and memory areas, the negative effect of the interaction between stressed overlayers and dislocation defects may be avoided or at least significantly reduced in the memory areas, thereby increasing production yield and stability of the memory areas.

Semiconductor device having stressed etch stop layers of different intrinsic stress in combination with PN junctions of different design in different device regions

Methods for forming asymmetric gate structures comprising spacer elements disposed on the opposed sides of a gate electrode and having a different width are disclosed. The asymmetric gate structures are employed to form an asymmetric design of a halo region and extension regions of a field effect transistor using a symmetric implantation scheme, or to further enhance the effectiveness of asymmetric implantation schemes. The transistor performance may be significantly enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the PN junction due to the provision of the halo region, whereas the drain overlap may be significantly reduced or may even be completely avoided to further enhance the transistor performance.

Gate structure and a transistor having asymmetric spacer elements and methods of forming the same

By using a disposable spacer approach for forming drain and source regions prior to an amorphization process for re-crystallizing a semiconductor region in the presence of a stressed spacer layer, possibly in combination with enhanced anneal techniques, such as laser and flash anneal processes, a more efficient strain-generating mechanism may be provided. Furthermore, the spacer for forming the metal silicide may be provided with reduced width, thereby positioning the respective metal silicide regions more closely to the channel region. Consequently, an overall enhanced performance may be obtained on the basis of the above-described techniques.

Technique for forming a strained transistor by a late amorphization and disposable spacers

A semiconductor structure comprising a first transistor element and a second transistor element is provided. Stress in channel regions of the first and the second transistor element is controlled by forming stressed layers having a predetermined stress over the transistors. The stressed layers may be used as etch stop layers in the formation of contact vias through an interlayer dielectric formed over the transistors.

Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regions

A semiconductor device manufacturing method is provided where a device structure is formed on top of a wafer that comprises a backside semiconductor substrate, a buried insulator layer and a top semiconductor layer. Then, an etch stop layer is formed upon the wafer that carries the device structure, and a window is formed in the etch stop layer. Further, a dielectric layer is formed upon the etch stop layer that has the window. Then, a first contact hole through the dielectric layer and the window down to the backside semiconductor substrate is simultaneously etched with at least one second contact hole through the dielectric layer down to the device structure. The wafer may be a silicon-on-insulator (SOI) wafer, and the etch stop layer and the dielectric layer may be formed by depositing silicon oxynitride and tetraethyl orthosilicate (TEOS), respectively. The device structure may be a CMOS transistor structure.

Simultaneous formation of device and backside contacts on wafers having a buried insulator layer

In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches, wherein a non-oxidizable mask is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner rounding and thus mechanical stress. Therefore, for a specified type of circuit elements, the characteristics of the corresponding isolation trenches may be tailored to achieve an optimum device performance.

Method of manufacturing a trench isolation structure for a semiconductor device with a different degree of corner rounding

In an SOI diode structure, the conventional transistor-like MOS configuration is eliminated by replacing the polysilicon line by a completely dielectric region. This region may be used as an implantation mask to control a dopant gradient of a PN-junction that forms below the dielectric region. Moreover, during the salicide process, the dielectric region prevents the PN-junction from being shorted. Thus, a depletion of the active region caused by the MOS structure may be avoided. Therefore, the functioning of the PN-junction is maintained even for extremely thin semiconductor layers.

Diode structure for SOI circuits

A semiconductor device comprises a field effect transistor and a passive capacitor, wherein the dielectric layer of the capacitor is comprised of a high-k material, whereas the gate insulation layer of the field effect transistor is formed of an ultra thin oxide layer or oxynitride layer so as to provide for superior carrier mobility at the interface between the gate insulation layer and the underlying channel region. Since carrier mobility in the capacitor is not of great importance, the high-k material allows the provision of high capacitance per unit area while featuring a thickness sufficient to effectively reduce leakage current.

Semiconductor device including a field effect transistor and a passive capacitor having reduced leakage current and an improved capacitance per unit area

A method comprises a &ldquo;two-step&rdquo; formation of a front side substrate contact in an FET formed over a buried insulator layer on a substrate, thereby avoiding the difficulties and problems involved in etching openings of high aspect ratio through a stack of different materials, as in a conventional front side substrate contact opening.

Method of forming a substrate contact in a field effect transistor formed over a buried insulator layer

In a semiconductor device including one or more semiconductor containing lines, such as gate electrodes of transistor elements, and/or active areas, sidewall spacer elements of the one or more semiconductor containing lines include a conductive layer that also covers a surface portion of the lines and extends to another semiconductor containing line or an active region to serve as a local interconnect. The sidewall spacer process sequence is modified to obtain the local interconnects along with the sidewall spacers without unduly contributing to process complexity. The conductive layers in the sidewall spacer elements, which may preferably comprise a metal, significantly improve the overall conductivity of these lines. Thus, the present invention offers increased design flexibility and the potential of increasing feature density.

Semiconductor device having an improved local interconnect structure and a method for forming such a device

There is provided a semiconductor device comprising an insulating layer which is partly formed of porous material, and a method for fabricating the device. A stray capacitance of adjacent wiring lines is significantly reduced by reducing the amount of material, i.e., by using porous material in the insulating layer of a metallization layer. In one embodiment, the porous layer may be fabricated separately on a further substrate and is subsequently transferred to the product wafer while the further substrate and the product wafer are appropriately aligned to each other. In this way, fabrication of complete metallization layers having a reduced dielectric constant in advance or concurrently with the product wafer carrying the MOS structure is possible. Due to the reduced capacitance of the wiring lines of the metallization layer, signal performance and/or power consumption of an integrated circuit is improved.

Semiconductor device having a reduced signal processing time and a method of fabricating the same

There is provided a semiconductor device comprising, for example, a MOS structure having a low electrical resistance in contacts and local interconnects, and a method for fabricating the device. When openings are formed in a dielectric region of a MOS structure, the thin metal silicide layer on top of a drain/source region is diminished due to the limited selectivity of the etch process and the need to over-etch to obtain appropriate electrical contacts. Consequently, the contact resistance is increased resulting in an increased contact resistance. Therefore, a bilayer metal is deposited on the metal silicide layer and the surface of the openings, wherein the metal layer that is in contact with the metal silicide layer is preferably the same metal as the metal of the metal silicide layer. In a subsequent annealing process, the metal of the bilayer partially converts into metal silicide, thereby increasing the initial metal silicide layer and concurrently reducing the contact resistance.

Growing community of inventors

Dresden, Germany

Gert Burbach