Tokyo Electron Limited

International Business Machines Corporation

Tokyo Electron Limi Ted

Gerrit J Leusink

Kandabara N Tapily

Kai-Hung Yu

Robert Daniel Clark

Cory Wajda

Kenji Suzuki

Emmanuel P Guidotti

Jeffrey Smith

Anton J deVillers

Joseph T Hillman

Masamichi Hara

Kaoru Maekawa

Takahiro Hakamata

Daisuke Kuroiwa

Fenton Read McFeely

David L O'Meara

Daniel J Fulford

Soo Doo Chae

Nicholas Joy

Gyanaranjan Pattanaik

Sandra Guy Malhotra

Tadahiro Ishizaka

Mirko Vukovic

Subhadeep Kal

Ronald W Nasman

Hoyoung Kang

Rodney Lee Robison

Tugrul Yasar

Michael S Ameen

Hiroaki Niimi

John Stephen Drewery

Jozef Brcka

Robert F Foster

Toshio Hasegawa

Douglas A Webb

Glyn J Reynolds

Rene E LeBlanc

Stanislaw Kopacz

Robert Clark Rowan, Jr

Michael James Grapperhaus

Dina Triyoso

Michael G Ward

Ying Trickett

Naoki Watanabe

Akiteru Ko

Angelique Denise Raley

Hideaki Yamasaki

Einstein Noel Abarra

Takashi Matsumoto

Eric Chih-Fang Liu

Lior Huli

Kunihiro Tada

Yun Han

Katie Lutker-Lee

Hiroki Maehara

Yusaku Kashiwagi

Mihaela Ioana Popovici

Steven P Caliendo

Hiroyuki Nagai

Lars-Ake Ragnarsson

Ian Colgan

Henan Zhang

Shihsheng Chang

Masanobu Igeta

Ioan Domsa

David Hurley

Corey Lemley

Barry Clarke

Hirokazu Aizawa

Satoru Nakamura

Gerhardus Van Der Linde

Hiroaki Kawasaki

Patrick Hughes

Maciej Burel

Emmanuel Guidotti

Manabu Oie

Hisashi Higuchi

Chihiro Tamura

Jerry Yeh

Tayler Bao

Robert R Young, Jr

Eric Chih Fang Liu

David Rosenthal

Yuuki Kikuchi

Robert Clark

Fenton R Mcfeely

Embodiments of methods are provided for thermal dry etching of a ruthenium (Ru) metal layer. In the disclosed embodiments, a substrate containing a Ru metal layer formed thereon is exposed to a gas pulse sequence, while the substrate is held at a relatively high substrate temperature (e.g., a temperature greater than or equal to about 160° C.), to provide thermal etching of the Ru metal layer. As described further herein, the gas pulse sequence may generally include a plurality of gas pulses, which are supplied to the substrate sequentially with substantially no overlap between gas pulses. The gas pulses supplied to the substrate form: (i) volatile reaction products that are vaporized from the Ru surface, and (ii) non-volatile oxide surface layers that are removed from the Ru surface by the next gas pulse, resulting in atomic layer etching (ALE) of the Ru metal layer.

Thermal etching of ruthenium

A method of processing a substrate that includes: etching a recess in the substrate using a metal hard mask (MHM) layer as an etch mask, the substrate including a dielectric layer over a conductive layer the includes a first conductive material, a portion of the MHM layer remaining over top surfaces of the dielectric layer after the etching; depositing a sacrificial fill over the substrate to at least partially fill the recess; removing the remaining portion of the MHM layer to expose the top surfaces while protecting the recess with the sacrificial fill; removing the sacrificial fill from the recess after removing the MHM layer, the removing of the sacrificial fill including exposing a portion of the conductive layer; and depositing a second conductive material to fill the recess, the depositing of the second conductive material providing an electrical connection between the conductive layer and the second conductive material.

Metal hard mask integration

A method of processing a substrate that includes: loading the substrate in a processing system, the substrate including a metal having a metal surface and a first dielectric material having a dielectric material surface, the metal surface and the dielectric material surface being at the same level; etching the metal to form a recessed metal surface below the dielectric material surface; selectively forming a self-assembled monolayer (SAM) on the recessed metal surface using a spin-on process; and depositing a dielectric film including a second dielectric material on the dielectric material surface.

Selective film formation using a self-assembled monolayer

A method of forming a metal superlattice structure includes depositing, on a substrate, a layer of a first metal with face-centered-cubic (fcc) crystal structure. The method further includes depositing a layer of ruthenium (Ru) metal with fcc crystal structure on the layer of the first metal. The layer of the first metal may cause the layer of ruthenium metal to have fcc crystal structure.

Conductive superlattice structures and methods of forming the same

An apparatus for depositing films on a backside of a substrate includes a processing chamber and a substrate support having an annular support surface. A first gas distribution unit includes a plurality of gas delivery openings arranged along the backside surface of the substrate and configured to direct plasma deposition gas to the backside surface. A second gas distribution unit is configured to flow a second gas into the processing chamber such that the front side surface of the substrate is exposed to the second gas. A controller is configured to control flow of the plasma deposition gas from the first gas distribution unit, flow of the second gas from the second gas distribution unit a vacuum system. The controller maintains a gas pressure differential between the front side surface and the backside surface of the substrate sufficient to prevent passage of the deposition gas from the backside surface.

System for backside deposition of a substrate

A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.

Method for filling recessed features in semiconductor devices with a low-resistivity metal

Techniques herein include a process chamber for depositing thin films to backside surfaces of wafers to reduce wafer bowing and distortion. A substrate support provides an annular perimeter seal around the bottom and/or side of the wafer which allows the majority of the substrate backside to be exposed to a process environment. A supported wafer separates the chamber into lower and upper chambers that provide different process environments. The lower section of the processing chamber includes deposition hardware configured to apply and remove thin films. The upper section can remain a chemically inert environment, protecting the existing features on the top surface of the wafer. Multiple exhausts and differential pressures are used to prevent deposition gasses from accessing the working surface of a wafer.

A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.

Semiconductor processing systems with in-situ electrical bias

A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.

A processing method includes receiving a substrate containing a base layer having a mandrel pattern formed thereon containing a number of features, conformally depositing a silicon oxide film over the mandrel pattern by coating surfaces of the substrate with a metal-containing catalyst layer, and in the absence of any oxidizing and hydrolyzing agent, exposing the substrate to a process gas containing a silanol gas at a substrate temperature selected to yield a preferred level of stress in the silicon oxide film. The method further includes removing the silicon oxide film from upper surfaces of the mandrel pattern and lower surfaces adjacent the mandrel pattern to leave behind silicon oxide sidewall spacers on sidewalls of the mandrel pattern, and removing the mandrel pattern from the substrate to leave behind the silicon oxide sidewall spacers that form a new pattern having double the number of features of the removed mandrel pattern.

Method for forming and using stress-tuned silicon oxide films in semiconductor device patterning

Aspects of the disclosure provide a method for forming a semiconductor apparatus. The method includes forming a first field-effect transistor (FET) that includes a first gate on a substrate of the semiconductor apparatus. The method includes forming a second FET that is stacked on the first FET along a direction substantially perpendicular to the substrate and includes a second gate. The method includes forming a first routing track and a second routing track that is electrically isolated from the first routing track. Each of the first and second routing tracks is provided on a routing plane stacked on the second FET along the direction. A first conductive trace configured to conductively couple the first gate of the first FET to the first routing track can be formed. A second conductive trace configured to conductively couple the second gate of the second FET to the second routing track can be formed.

Semiconductor apparatus having stacked gates and method of manufacture thereof

A method of area selective deposition for cap layer formation in advanced semiconductor contacts. The method includes providing a planarized substrate including a first dielectric layer and a first metal layer, oxidizing a surface of the first metal layer to form an oxidized metal layer, and selectively depositing a second dielectric layer on the oxidized metal layer. The selectively depositing the second dielectric layer can include moving the planarized substrate below a gas inlet dispensing a deposition gas during a spatial vapor phase deposition process, where the deposition gas is preferentially exposed to the oxidized metal layer extending above a surface of the first dielectric layer.

Area selective deposition for cap layer formation in advanced contacts

A semiconductor device is provided. The semiconductor device can have a substrate including dielectric material. A plurality of narrow interconnect openings can be formed within said dielectric material. In addition, a plurality of wide interconnect openings can be formed within said dielectric material. The semiconductor device can include a first metal filling the narrow interconnect openings to form an interconnect structure and conformally covering a surface of the wide interconnect openings formed in the dielectric material, and a second metal formed over the first metal and encapsulated by the first metal to form another interconnect structure within the wide interconnect openings.

Interconnect structure and method of forming the same

A method of forming a nanowire device includes providing a substrate containing nanowires between vertical spacers, selectively depositing a high-k film on the nanowires relative to the vertical spacers, and selectively depositing a metal-containing gate electrode layer on the high-k film relative to the vertical spacers. The method can further include selectively depositing a dielectric material on the vertical spacers prior to selectively depositing the high-k film, where the dielectric material has a lower dielectric constant than the high-k film.

Method for forming a nanowire device

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Rexford, NY, United States of America

Gerrit J Leusink