Infineon Technologies Austria Ag

Infineon Technologies Ag

Gerhard Prechtl

Clemens Ostermaier

Oliver Haeberlen

Oliver Häberlen

Gilberto Curatola

Andreas Peter Meiser

Thomas Detzel

Klaus Schiess

Thomas Krotscheck Ostermann

Bernhard Zojer

Matthias Strassburg

Hans Peter Felsl

Gebhart Dippold

Severin Kampl

Manuel Stabentheiner

Horst Schäfer

Ralf Otremba

Eung San Cho

Oliver Blank

Kennith Kin Leong

Dirk Ahlers

Adrian Finney

Michael Stadtmueller

Mohamed Imam

Guenter Denifl

Gianmauro Pozzovivo

Hyeongnam Kim

Simone Lavanga

David Kammerlander

Gerhard Nöbauer

Nils Jensen

Marius Aurel Bodea

Bhargav Pandya

Jens Ulrich Heinle

Luca Sayadi

Balamurugan Karunamurthy

Maria Reiner

Peter Lagger

Josef Schellander

Marcel Kreuzberg

Nicholas Dellas

Joachim Schönle

Juergen Bostjancic

Gerhard Raczynski

An integrated circuit includes a semiconductor substrate, first and second doping regions in the substrate, a first insulating layer on a first surface of the semiconductor substrate, the first insulating layer having first and second openings above the first and second doping regions, a polysilicon layer on the first insulating layer, the polysilicon layer having first and second openings above the first and second openings of the first insulating layer, a second insulating layer on the polysilicon layer and having first and second openings above the first and second openings of the polysilicon layer, a first contact element disposed in the first openings, a second contact element disposed in the second openings, the first and second contact elements being in contact with the first and second doping regions.

Integrated circuit and bipolar transistor

A semiconductor device includes: a device formed in a III-V semiconductor body; metal layer(s) above the III-V semiconductor body; an interlayer dielectric adjacent each metal layer; vias electrically connecting each metal layer to the device formed in the III-V semiconductor body; a passivation layer touching and being supported by a top surface of the III-V semiconductor body, the lowermost interlayer dielectric touching and being supported by a top surface of the passivation layer, the passivation layer being an ineffective barrier against diffusion of water, water ions, sodium ions and potassium ions into the III-V semiconductor body; and a barrier interposed between a first oxide layer and a second oxide layer of the lowermost interlayer dielectric. The barrier is configured to prevent water, water ions, sodium ions and potassium ions from diffusing into the first oxide layer of the lowermost interlayer dielectric and which is immediately below the barrier.

Water and ion barrier for III-V semiconductor devices

An electronic circuit and a method are disclosed. The electronic circuit includes: a first transistor device having a load path between a first load path node and a second load path node; and a clamping circuit connected to the load path of the first transistor device. The clamping circuit includes: a second transistor device having a load path connected in parallel with the load path of the first transistor device, and a control node; and a drive circuit configured to drive the second transistor device. The drive circuit includes a clamping element and a resistor connected in series between the first and second load path nodes of the first transistor device. The drive circuit is configured to drive the second transistor device dependent on a voltage across the resistor. The first transistor device and the clamping circuit are integrated in a same semiconductor die.

Electronic circuit with a transistor device and a clamp circuit and method

A method includes providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels, forming a gate fin by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels, providing source and drain contacts that are electrically connected to each one of the plurality of two-dimensional charge carrier gas channels, providing a gate structure that is configured to control a conductive connection between the source and drain contacts, wherein providing the gate structure includes forming a layer of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and forming a conductive gate electrode on top of the layer of doped type III-nitride semiconductor material.

High electron mobility transistor with doped semiconductor region in gate structure

A high-electron-mobility transistor comprises a semiconductor body comprising a barrier region and a channel region that forms a heterojunction with the barrier region such that a two-dimensional charge carrier gas channel is disposed in the channel region, source and drain electrodes disposed on the semiconductor body and laterally spaced apart from one another, a gate structure disposed on the semiconductor body and laterally between the source and drain electrodes, the gate structure being configured to control a conduction state of two-dimensional charge carrier gas, and a first dielectric region that is disposed along the upper surface of the semiconductor body in a lateral region that is between the gate structure and the drain electrode, wherein the first dielectric region comprises aluminum and oxide, and wherein first dielectric region comprises a first end that faces and is laterally spaced apart from the gate structure.

Type III-V semiconductor device with structured passivation

In an embodiment, a Group III nitride-based transistor device, includes a first Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length l, and 0 nm≤l≤200 nm.

Group III nitride-based transistor device

A semiconductor device includes a main bi-directional switch formed on a semiconductor substrate and having first and second gates, a first source electrically connected to a first voltage terminal, a second source electrically connected to a second voltage terminal, and a common drain. The semiconductor device further includes a discharge circuit having a plurality of individual transistors or an auxiliary bi-directional switch monolithically integrated with the main bi-directional switch and connected in a common source configuration to the semiconductor substrate. The plurality of individual transistors or the auxiliary bi-directional switch includes a first drain connected to the first source of the main bi-directional switch, a second drain connected to the second source of the main bi-directional switch, and first and second gates each decoupled from gate drive circuitry so that the first and the second gates are controlled at least passively and based on a state of the main bi-directional switch.

Semiconductor device having a bidirectional switch and discharge circuit

An enhancement mode Group III nitride-based transistor device includes a body having a first surface and a Group III nitride barrier layer arranged on a Group III nitride channel layer and forming a heterojunction therebetween. A first cell field includes transistor cells and an edge region. Each transistor cell includes source, gate and drain fingers extending substantially parallel to one another on the first surface in a longitudinal direction. The gate finger, arranged laterally between the source and drain fingers, includes a p-doped Group III nitride finger arranged between a metallic gate finger and the first surface. The edge region surrounds the transistor cells and includes an edge termination structure having an isolation ring and a p-doped Group III nitride runner. The isolation ring locally interrupts the heterojunction. The runner, extending transversely to the longitudinal direction, is located laterally between the isolation ring and an end of the drain finger.

Enhancement mode transistor device

Enhancement mode Group III nitride-based transistor device

In an embodiment, a Group III nitride-based transistor device, includes a first. Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first. Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length l, and 0 nm&#x2264;l&#x2264;200 nm.

Group III nitride-based transistor device and method of fabricating a gate structure for a group III nitride-based transistor device

A transistor device includes a gate fin that is a segment of a semiconductor body disposed between a pair of gate trenches formed in an upper surface of the semiconductor body, a plurality of two-dimensional charge carrier gas channels disposed at different vertical depths within the gate fin, source and drain contacts arranged on either side of the gate fin in a current flow direction of the gate fin, the source and drain contacts each being electrically connected to each one of the two-dimensional charge carrier gas channels, and a gate structure that is configured to control a conductive connection between the source and drain contacts. The gate structure includes a region of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and a conductive gate electrode formed over the region of doped type III-nitride semiconductor material.

A high-electron-mobility semiconductor device includes: a buffer region having first, second and third cross-sections forming a stepped lateral profile, the first cross-section being thicker than the third cross-section and comprising a first buried field plate disposed therein, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections; and a barrier region of substantially uniform thickness extending along the stepped lateral profile of the buffer region, the barrier region being separated from the first buried field plate by a portion of the buffer region. The buffer region is formed by a first semiconductor material and the barrier region is formed by a second semiconductor material. The first and second semiconductor materials have different band-gaps such that an electrically conductive channel including a two-dimensional charge carrier gas arises at an interface between the buffer and barrier regions due to piezoelectric effects.

High-electron-mobility transistor having a buried field plate

A semiconductor device includes a group III-semiconductor-nitride-based channel layer, a group III-semiconductor-nitride-based barrier layer formed on the channel layer, a two-dimensional electron gas channel formed in the channel layer, a first current electrode and a second current electrode formed on the barrier layer and laterally spaced from each other, and a gate structure formed on the barrier layer between the first and second current electrodes. The barrier layer has a symmetrically shaped recess between the first and second current electrodes, the symmetrically shaped recess including a first recess portion formed in a part of an upper surface of the barrier layer and a second recess portion formed within the first recess portion. The gate structure includes a group III-semiconductor-nitride-based doped layer that fills the symmetrically shaped recess and an electrically conductive gate electrode formed on an upper side of the doped layer that is opposite from the barrier layer.

Semiconductor device

A method of producing a semiconductor component is provided. The method includes providing a silicon substrate having a &#x3c;111&#x3e;-surface defining a vertical direction, forming in the silicon substrate at least one electronic component, forming at least two epitaxial semiconductor layers on the silicon substrate to form a heterojunction above the &#x3c;111&#x3e;-surface, and forming a HEMT-structure above the &#x3c;111&#x3e;-surface.

Method for producing an integrated heterojunction semiconductor device

Growing community of inventors

Rosegg, Austria

Gerhard Prechtl