Infineon Technologies Ag

International Business Machines Corporation

Other

United Microelectronics Co.

Gerald R Friese

Hans-Joachim Barth

Erdem Kaltalioglu

Petra Felsner

Mark Hoinkis

Andy Cowley

Werner Robl

Matthias Hierlemann

Axel Brintzinger

Dennis J Warner

William Thomas Motsiff

Kenneth Jay Stein

Michael D Armacost

Andreas Augustin

Thomas Goebel

John E Heidenreich, Iii

Lloyd G Burrell

Mohammed Fazil Fayaz

Pak Leung

Gary Robert Hueckel

Michael Stetter

An embodiment of a MIM capacitor includes a first insulating layer formed over a wafer and a first capacitor plate formed over the wafer within the first insulating layer. The MIM capacitor further includes a second insulating layer formed over the first insulating layer, a capacitor dielectric formed over the first capacitor plate within the second insulating layer and a second capacitor plate formed over the capacitor dielectric within the second insulating layer. A recess is formed in the second capacitor plate below an upper surface of the second insulating layer and a catalytic activation layer is formed in the recess.

MIM capacitors with catalytic activation layer

A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.

Method and apparatus of stress relief in semiconductor structures

A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.

MIM capacitor with a cap layer over the conductive plates

In a semiconductor integrated circuit device, thermo-mechanical stresses on the vias can be reduced by introducing a stress relief layer between the vias and a hard dielectric layer that overlies the vias.

Stress-relief layer for semiconductor applications

Methods of forming MIM capacitors

The act of blowing an unpassivated electrical fuse (for example, fuse) using a laser can result in the splattering of the fuse material and result in electrical short circuits. A blast barrier (for example blast barrier) formed around an area of the fuse that is blown by the laser helps to contain the splattering of the fuse material. The blast barrier may be formed from the same material as the fuses themselves and, therefore, can be created in the same fabrication step.

Reduced splattering of unpassivated laser fuses

A bond pad structure formed over a predetermined area of an IC substrate comprising quickly and easily removable redundancy and passivation layers upon lithography and plasma etching in a plasma containing Cl, the bond structure comprises: a liner or lower metal layer formed on a predetermined area of the IC substrate; an aluminum-based metal layer formed on the liner layer as the last metal layer for bond purposes; a tungsten based redundancy layer formed on top of the aluminum-based last metal layer; and a passivation layer formed over the IC substrate and on the tungsten based redundancy layer.

Bond pad structure comprising tungsten or tungsten compound layer on top of metallization level

A parallel plate capacitor in copper technology is formed in an area that has no copper below it (within 0.3 &mgr;m) with a bottom etch stop layer, a composite bottom plate having an aluminum layer below a TiN layer, an oxide capacitor dielectric, and a top plate of TiN; in a process that involves etching the top plate to leave a capacitor area, etching the bottom plate to a larger bottom area having a margin on all sides; depositing an interlayer dielectric having a higher material quality below the top surface of the capacitor top plate; opening contact apertures to the top and bottom plates and to lower interconnect to a two step process that partially opens a nitride cap layer on the lower interconnect and the top plate while penetrating the nitride cap layer above the bottom plate, then cutting through the capacitor dielectric and finishing the penetration of the nitride cap layer.

Metal-insulator-metal capacitor in copper

FBEOL process for Cu metallizations free from Al-wirebond pads

Disclosed is a method of ball grid array packaging, comprising the steps of providing a semiconductor die having a metal conductors thereon, covering said metal conductors with an insulative layer, etching through said insulative layer so as to provide one or more openings to said metal conductors, depositing a compliant material layer, etching through said compliant material layer so as to provide one or more openings to said metal conductors, depositing a substantially homogenous conductive layer, patterning said conductive layer so as to bring at least one of said metal conductors in electrical contact with one or more pads, each said pad comprising a portion of said conductive layer disposed upon said compliant material, and providing solder balls disposed upon said pads. Also disclosed is the apparatus made from the method.

Method of eliminating back-end rerouting in ball grid array packaging

A process for forming fusible links in an integrated circuit includes forming the fusible link in the last metallization layer. The process can be employed in the fabrication of integrated circuits employing copper metallization and low k dielectric materials. The fusible link is formed in the last metallization layer and may be formed simultaneously with the bonding pad areas.

Process for forming fusible links

A method of making a metal-insulator-metal (MIM) capacitor ( ) having self-passivating plates ( ). A liner ( ) is deposited on a workpiece ( ) and dielectric ( ). A conductive layer ( ) is deposited and annealed to form dopant-rich region ( ). Insulating region ( ) is formed on exposed portions of dopant-rich region ( ) by exposure to atmosphere or oxygen. Capacitor dielectric layer ( ) is disposed over the first capacitive plate ( ). A second capacitive plate ( ) is formed over the first capacitive plate ( ) and capacitor dielectric layer ( ). The second capacitive plate ( ) is annealed to form dopant-rich region ( ) and exposed to atmosphere or oxygen to form insulating region ( ). Optional seed layer ( ) may be deposited prior to the formation of the first capacitive plate ( ).

Growing community of inventors

Munich, Germany

Gerald R Friese