Infineon Technologies Ag

Intel Corporation

Intel Mobile Communications Gmbh

Intel Deutschland Gmbh

Siemens Aktiengesellschaft

Gerald Ofner

Thorsten Meyer

Christian Geissler

Bernd Goller

Reinhard Mahnkopf

Robert-Christian Hagen

Sven Albers

Andreas Augustin

Stefan Wein

Alexander Heinrich

Christian Stuempfl

Kai Chong Chan

Josef Thumbs

Horst Theuss

Michael Bauer

Georg Seidemann

Bernd Waidhas

Andreas Wolter

Stephan Bradl

Peter Scherl

Stefan Miethaner

Christian Mueller

Holger Wörner

Mary Teo

Charles Wee Ming Lee

Recai Sezi

Rainer Leuschner

Holger Woerner

Teodora Ossiander

Reinhard Hess

Ai Min Tan

Swain Hong Yeo

Frank Zudock

Pei Siang Lim

Christian St&uuml;mpfl

Holger W&ouml;rner

Robert L Sankman

Hans-Joachim Barth

Sanka Ganesan

Simon Jerebic

Klaus Reingruber

Thomas Bemmerl

Peter Strobel

Philipp Riess

Hermann Vilsmeier

Stephan Stoeckl

Markus Fink

Edward Fürgut

Christian Birzer

Reinhard Golly

Robert Christian Hagen

Christian Stümpfl

Bernd Ebersberger

Khoon Lam Chua

A method of forming a semiconductor package includes providing a panel, providing one or more metal layers on an upper surface of the panel, forming a die pad and bond pads from the one or more metal layers, the die pad being adjacent to and spaced apart from the bond pads, attaching a die to the die pad, forming electrical connections between the die and the bond pads, encapsulating the die and the electrical connections with an electrically insulating mold compound, removing portions of the panel, and exposing the die pad and the bond pads after encapsulating the die.

Flat lead package formation method

A method of producing packaged semiconductor devices includes providing a first packaging substrate panel, providing a second packaging substrate panel, and moving the first and second packaging substrate panels through an assembly line that comprises a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner. The first and second packaged semiconductor devices differ with respect to at least one of: lead configuration, and encapsulant configuration.

Multi-purpose non-linear semiconductor package assembly line

Disclosed herein are integrated circuit (IC) packages, and related structures and techniques. In some embodiments, an IC package may include: a die; a redistribution structure, wherein the die is coupled to the redistribution structure via first-level interconnects and solder; a solder resist; and second-level interconnects coupled to the redistribution structure through openings in the solder resist.

Integrated circuit packages

A package comprising a chip carrier, an electronic chip on the chip carrier, a clip on the electronic chip, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive vertical connection structure provided separately from the clip and electrically connecting the chip carrier with the clip.

Package with vertical interconnect between carrier and clip

A method of producing packaged semiconductor devices includes providing a first packaging substrate panel. A second packaging substrate panel is provided. The first and second packaging substrate panels are moved through an assembly line that includes a plurality of package assembly tools using a control mechanism. First type packaged semiconductor devices are formed on the first packaging substrate panel and second type packaged semiconductor devices are formed on the second packaging substrate panel. The second type packaged semiconductor device is different than the first type packaged semiconductor device. The control mechanism moves both of the first and packaging substrate panels through the assembly line in a non-linear manner.

A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.

Microelectronic package having a passive microelectronic device disposed within a package body

In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

Microelectromechanical system (MEMS) on application specific integrated circuit (ASIC)

A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.

Flexible band wearable electronic device

A package-on-package stacked microelectronic structure comprising a pair of microelectronic packages attached to one another in a flipped configuration. In one embodiment, the package-on-package stacked microelectronic structure may comprise a first and a second microelectronic package, each comprising a substrate having at least one package connection bond pad formed on a first surface of each microelectronic package substrate, and each having at least one microelectronic device electrically connected to the each microelectronic package substrate first surface, wherein the first and the second microelectronic package are connected to one another with at least one package-to-package interconnection structure extending between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad.

Package-on-package stacked microelectronic structures

Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.

Integrated circuit package

Passive electrical devices are described with a polymer carrier. In one example, a conductive layer is formed over a polymer substrate in a pattern to form a passive electrical device and at least two terminals of the device. A plurality of external connection pads are connected to the terminals of the device.

Passive electrical devices with a polymer carrier

A chip arrangement may include: a mold compound; and a microelectromechanical systems device at least partially embedded in the mold compound.

Chip arrangement and method for manufacturing a chip arrangement

Growing community of inventors

Wuppertal, Germany

Gerald Ofner