Taiwan Semiconductor Manufacturing Comp. Ltd.

Georgios Vellianitis

Gerben Doornbos

Marcus Johannes Henricus Van Dal

Blandine Duriez

Martin Christopher Holland

Mark Van Dal

Mauricio Manfrini

Matthias Passlack

Richard Kenneth Oxland

Sai-Hooi Yeong

Chun-Chieh Lu

Timothy Vasen

Yu-Ming Lin

Krishna Kumar Bhuwalka

Tsung-Lin Lee

Feng Yuan

Chien-Hsun Wang

Gilberto Curatola

Nader Akil

Oreste Madia

Marcus Van Dal

Kyriaki Fotopoulou

Ravindranath Droopad

Shih-Wei Wang

Shih Wei Wang

Yee-Chaung See

Gerben Doombos

Ferroelectric field effect transistors are in a three-dimensional structure that includes vertical columns. Source/drain electrodes are provided by horizontal conductive layers that are interleaved with dielectric layers. Channels for the FeFETs in each vertical column are provided by a continuous semiconductor layer, e.g., a vertical strip of semiconductor. Another vertical strip may provide the ferroelectric layers for the FeFETs in the vertical column. The gate electrodes are provided by a control gate structure that connects the gate electrodes in parallel. The source/drain electrodes of multiple vertical columns may be connected in parallel. The source/drain electrodes of multiple tiers may also be connected in parallel. This structure provides high area density, adds an extra degree of freedom in circuit design, and lends itself to the use of oxide semiconductor channels.

Vertically stacked FeFETs with common channel

An exemplary method includes forming an opening in an interlevel dielectric (ILD) layer. The opening in the ILD layer exposes a doped epitaxial layer. The method further includes performing an in-situ doping deposition process, an annealing process, and an etching process to form a doped semiconductor layer over the doped epitaxial layer. The doped semiconductor layer partially fills the opening. The method further includes forming a metal-comprising structure that fills a remainder of the opening. The metal-comprising structure is disposed over a top and sidewalls of the doped epitaxial layer. The doped semiconductor layer is disposed between the metal-comprising structure and the top of the doped epitaxial layer and between the metal-comprising structure and the sidewalls of the doped epitaxial layer. The in-situ deposition process may implement a temperature less than about 350° C. The doped epitaxial layer includes p-type dopant (e.g., boron), and the doped semiconductor layer includes gallium.

Multigate device having reduced contact resistivity

A semiconductor structure includes a substrate; a resistance variable layer disposed over the substrate; a gate structure disposed over the resistance variable layer; a dielectric layer disposed over the resistance variable layer and surrounding the gate structure; a first contact plug disposed over the resistance variable layer and extending through the dielectric layer; and a second contact plug disposed over the resistance variable layer and opposite to the first contact plug and extending through the dielectric layer, wherein the resistance variable layer is semiconductive and ferroelectric. A method of manufacturing a semiconductor structure is also disclosed.

Semiconductor structure and manufacturing method thereof

A ferroelectric device and a wave computing device are provided. The ferroelectric device includes a first electrode, a second electrode, a ferroelectric layer and a wave guide. The ferroelectric layer is disposed between the first and second electrodes, and configured to transduce an electrical wave signal to a varying mechanical stress by piezoelectricity, or vice versa. A first polarization state or a second polarization state opposite to the first polarization state is programmed in the ferroelectric layer. The wave guide is in contact with the ferroelectric layer, and configured to transmit a wave signal resulted from or resulting the varying mechanical stress. The wave signal is in phase with the electrical wave signal when the ferroelectric layer is programmed with the first polarization state. The wave signal is out of phase with the electrical wave signal when the ferroelectric layer is programmed with the second polarization state.

Ferroelectric device and wave computing device

A transistor may be provided by forming, in a forward order or in a reverse order, a gate electrode, a metal oxide liner, a gate dielectric, and an active layer over a substrate, and by forming a source electrode and a drain electrode on end portions of the active layer. The metal oxide liner comprises a thin semiconducting metal oxide material that functions as a hydrogen barrier material.

Access transistor including a metal oxide barrier layer and methods for forming the same

A field effect transistor may include an active layer containing an oxide compound material of at least two atomic elements including a first element of tin and a second element selected from Ge, Si, P, S, F, Ti, Cs, and Na and located over a substrate. The field effect transistor may further include a gate dielectric located on the active layer, a gate electrode located on the gate dielectric, and a source contact structure and a drain contact structure contacting a respective portion of the active layer. The oxide compound material may include at least germanium and tin. The oxide compound semiconductor material may be used as a p-type semiconductor material in BEOL structures.

Germanium tin oxide-containing semiconductor device and methods for forming the same

A transistor device and the manufacturing methods are described. The device includes a gate structure having a gate layer and a ferroelectric layer, source and drain terminals, and a crystalline channel portion. The source and drain terminals are disposed at opposite sides of the gate structure. The crystalline channel portion extends between the source and drain terminals. The source and drain terminals are disposed on the crystalline channel portion and the gate structure is disposed on the crystalline channel portion. The crystalline channel portion includes a first material containing a Group III element and a Group V element, the gate layer includes a second material containing a Group III element and a rare-earth element, and the ferroelectric layer includes a third material containing a Group III element, a rare-earth element and a Group V element.

Semiconductor device and method of fabricating the same

A ferroelectric memory device includes a multi-layer stack, a channel layer and a III-V based ferroelectric layer. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers of the multi-layer stack. The III-V based ferroelectric layer is disposed between the channel layer and the multi-layer stack, and includes at least one element selected from Group III elements, at least one element selected from Group V elements, and at least one element selected from transition metal elements.

Ferroelectric memory device and method of forming the same

A semiconductor structure includes a storage element layer and a selector. The selector is electrically coupled to the storage element layer, and includes a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer and a second conductive layer. The first insulating layer, the second insulating layer and the third insulating layer are stacked up in sequence, wherein the second insulating layer is sandwiched in between the first insulating layer and the third insulating layer, and the first insulating layer and the third insulating layer include materials with higher band gap as compared with a material of the second insulating layer. The first conductive layer is connected to the first insulting layer, and the second conductive layer is connected to the third insulating layer.

Semiconductor structure and method of forming the same

A method includes forming a first dielectric layer over a substrate; forming a first transistor over a first side of the first dielectric layer; removing the substrate to expose a second side of the first dielectric layer opposite to the first side of the second dielectric layer; and forming a second transistor over the second side of the first dielectric layer. Forming the first transistor includes forming a semiconductor layer over the first side of the first dielectric layer; forming a first gate structure over the semiconductor layer; and forming source/drain epitaxy structures on opposite sides of the first gate structure. Forming the second transistor includes forming a semiconductive oxide layer over the second side of the first dielectric layer; forming a second gate structure over the semiconductive oxide layer; and forming source/drain contacts over the semiconductive oxide layer and on opposite sides of the second gate structure.

Method for forming semiconductor device with transistors on opposite sides of a dielectric layer

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes an interconnect structure and an electrode layer formed over the interconnect structure. The semiconductor structure also includes a gate dielectric layer formed over the electrode layer and an oxide semiconductor layer formed over the gate dielectric layer. The semiconductor structure also includes an indium-containing feature covering a surface of the oxide semiconductor layer and a source/drain contact formed over the indium-containing feature.

Semiconductor structure with thin film transistor

In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure is formed. The fin structure includes a plurality of stacked structures each comprising a dielectric layer, a CNT over the dielectric layer, a support layer over the CNT. A sacrificial gate structure is formed over the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, the support layer is removed from each of the plurality of stacked structures in the source/drain opening, and a source/drain contact layer is formed in the source/drain opening. The source/drain contact is formed such that the source/drain contact is in direct contact with only a part of the CNT and a part of the dielectric layer is disposed between the source/drain contact and the CNT.

Method of manufacturing a field effect transistor using carbon nanotubes and a field effect transistor

A transistor includes a vertical stack containing, in order from bottom to top or from top to bottom, a gate electrode, a gate dielectric, and an active layer and located over a substrate. The active layer includes an amorphous semiconductor material. A crystalline source region including a first portion of a crystalline semiconductor material overlies, and is electrically connected to, a first end portion of the active layer. A crystalline drain region including a second portion of the crystalline semiconductor material overlies, and is electrically connected to, a second end portion of the active layer.

Transistors including crystalline raised active regions and methods for forming the same

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.

Ferroelectric channel field effect transistor

A manufacturing method of a complementary metal-oxide-semiconductor device includes forming semiconductor fins over a semiconductor substrate; forming nanosheets over the semiconductor substrate; forming a gate structure contacting the semiconductor fins and the nanosheets, where a contact area of the gate structure with the semiconductor fins extends mostly along a (110) crystallographic surface of a semiconductor material of the semiconductor fins, and a contact area of the gate structure with the nanosheets extends mostly along a (100) crystallographic surface of a semiconductor material of the nanosheets.

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Heverlee, Belgium

Georgios Vellianitis